Asr Error Handling - Fujitsu SPARC JPS1 Implementation Supplement Manual

TABLE P-18
Register Name
TPC
TNPC
TSTATE
WSTATE
VER
FSR
P.8.2

ASR Error Handling

The terminology used in
Column
Error Detect
Condition
Error Type
Correction
TABLE P-19
ASR Error Handling
TABLE P-19
ASR
Number Register Name
0
Y
1 —
2
CCR
3
ASI
4
TICK
182 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
Register Error Handling (Excluding ASRs and ASI Registers)
Error
RW Protect
RW Parity
RW Parity
RW Parity
RW Parity
R None
RW Parity
TABLE P-19
Term
always
AUG
InstAccess
_xxx
(I)AUG
_xxx
I(A)UG
W
trap
ADE
shows the handling of ASR errors.
RW Error Protect Error Detect Condition
RW Parity InstAccess
RW Parity Always
RW Parity Always
RW None —
Error Detect Condition
InstAccess
InstAccess
InstAccess
InstAccess
—
Always
is defined as follows:
Meaning
The error is detected while
(ASI_ERROR_CONTROL.UGE_HANDLER = 0) &&
(ASI_ERROR_CONTROL.WEAK_ED = 0)
The error is detected when the instruction accesses the
register.
The error is indicated by ASI_UGESR.IAUG_xxx = 1, and
the error is an autonomous urgent error.
The error is indicated by ASI_UGESR.IAUG_xxx = 1, and
the error is an instruction urgent error.
The error is removed by a full write to the register by an
instruction.
The error is removed by a full write to the register in the
hardware trap sequence.
async_data_error
Error Type
IUG_%R
IUG_%R
IUG_%R
—
Error Type Correction
IUG_TSTATE W
IUG_TSTATE W
IUG_TSTATE
W
IUG_TSTATE W
— —
IUG_%F
ADE
Correction
W
trap, W
ADE
trap, W
ADE
—
trap, W