Fujitsu SPARC JPS1 Implementation Supplement Manual page 198

Handling of ASI Register Errors (Continued)
TABLE P-20
ASI VA
Register Name
58 30
DMMU_TAG_ACCESS
16 16
58 38
DMMU_VA_WATCHPOINT
16 16
58 40
DMMU_PA_WATCHPOINT
16 16
58 48
DMMU_TSB_PEXT
16 16
58 50
DMMU_TSB_SEXT
16 16
58 58
DMMU_TSB_NEXT
16 16
59 —
DMMU_TSB_8KB_PTR
16
5A —
DMMU_TSB_64KB_PTR
16
5B —
DMMU_TSB_DIRECT_PTR
16
5C —
DTLB_DATA_IN
16
5D —
DTLB_DATA_ACCESS
16
5E —
DTLB_TAG_READ
16
5F —
DMMU_DEMAP
16
60 —
IIU_INST_TRAP
16
6E 00
EIDR
16 16
6F — parallel barrier assist
16
77 40 –
INTR_DATA0:7_W
16 16
88
INTR_DISPATCH_W
16
7F 40 –
INTR_DATA0:7_R
16 16
88
16
EF — Parallel barrier assist
16
Release 1.0, 1 July 2002
Error Error Detect
RW Protect Condition
RW Parity LDXA #D
RW Parity Enabled
LDXA
RW Parity Enabled
LDXA
RW Parity = DTSB_BASE
RW Parity = DTSB_BASE
R Parity = DTSB_BASE
R PP
LDXA
R PP
LDXA
R PP
LDXA
W Parity DTLB write
RW Parity
LDXA
DTLB write
R Parity
LDXA
W Parity DTLB write
RW Parity
LDXA
RW Parity Always
RW Parity always
AUG
LDXA
BV interface
W Gecc None
W Gecc store
R ECC
LDXA
intr_receive
RW Parity always
AUG
LDXA
BV interface
Error Type Correction
W (WotherD)
IUG_TSBP
(I)AUG_CRE W
I(A)UG_CRE
W
(I)AUG_CRE W
I(A)UG_CRE
W
W
I(A)UG_TSBCTXT
I(A)UG_TSBCTXT W
I(A)UG_TSBCTXT None
IUG_TSBP WotherD
IUG_TSBP WotherD
IUG_TSBP WotherD
IUG_DTLB DemapAll
DemapAll
IUG_DTLB
IUG_DTLB
DemapAll
IUG_DTLB DemapAll
DemapAll
IUG_DTLB
No match at error W
IAUG_CRE W
Not detected (#dv) W
(#dv) W
COREERROR
(I)AUG_CRE
None
— W
(I)AUG_CRE
W
(#dv) Interrupt
COREERROR
Receive
BUSY = 0
Not detected (#dv) W
(#dv) W
COREERROR
(I)AUG_CRE
None
F. Chapter P Error Handling 187