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TABLE C-1
Nbr
9
10–12
13
14–15
16
17
18
19
20–21
22
23
24
25
26–28
29
30
31
Release 1.0, 1 July 2002
SPARC64 V Implementation Dependencies (2 of 11)
SPARC64 V Implementation Notes
RDASR/WRASR privileged status
See A.50 and A.70 in Commonality for details of implementation-dependent
RDASR/WRASR instructions.
Reserved.
VER.impl
SPARC64 V
VER.impl = 5 for the
Reserved.
IU deferred-trap queue
SPARC64 V
neither has nor needs an IU deferred-trap queue.
Reserved.
Nonstandard IEEE 754-1985 results
SPARC64 V
flushes denormal operands and results to zero when
FSR.NS = 1. For the treatment of denormalized numbers, please refer to
Section B.6, Floating-Point Nonstandard Mode, on page 61 for details.
FPU version, FSR.ver
SPARC64 V
FSR.ver = 0 for
Reserved.
FPU TEM, cexc, and aexc
SPARC64 V
implements all bits in the TEM, cexc, and aexc fields in
hardware.
Floating-point traps
In
SPARC64 V
floating-point traps are always precise; no FQ is needed.
FPU deferred-trap queue (FQ)
SPARC64 V
neither has nor needs a floating-point deferred-trap queue.
RDPR of FQ with nonexistent FQ
Attempting to execute an RDPR of the FQ causes an
exception.
Reserved.
Address space identifier (ASI) definitions
The ASIs that are supported by
Address Space Identifiers.
ASI address decoding
SPARC64 V
supports all of the listed ASIs.
Catastrophic error exceptions
SPARC64 V
contains a watchdog timer that times out after no instruction
has been committed for a specified number of cycles. If the timer times out,
the CPU tries to invoke an
33
count to reach 2
, the processor enters error_state. Upon an entry to
error_state, the processor optionally generates a WDR reset to recover
from error_state.
processor.
.
SPARC64 V
are defined in Appendix L,
trap. If the counter continues to
async_data_error
F. Chapter C
illegal_instruction
Implementation Dependencies
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