Performance Monitor Overview; Sample Pseudocodes - Fujitsu SPARC JPS1 Implementation Supplement Manual

Q
F. A P P E N D I X
Performance Instrumentation
This appendix describes and specifies performance monitors that have been
implemented in the SPARC64 V processor. The appendix contains these sections:
Performance Monitor Overview on page 201
Performance Monitor Description on page 203
Q.1

Performance Monitor Overview

For the definitions of performance counter registers, please refer to Performance
Control Register (PCR) (ASR16) and Performance Instrumentation Counter (PIC) Register
(ASI 17) in Chapter 5 of Commonality.
Q.1.1

Sample Pseudocodes

Counter Clear/Set
The PICs are read/write registers (see Performance Instrumentation Counter (PIC)
Register (ASR 17) on page 22). Writing zero will clear the counter; writing any other
value will set that value. The following pseudocode procedure clears all PICs
(assuming privileged access):
Instruction Statistics on page 204
Trap-Related Statistics on page 206
MMU Event Counters on page 207
Cache Event Counters on page 208
UPA Event Counters on page 210
Miscellaneous Counters on page 211
201