Fujitsu SPARC JPS1 Specification Manuals

Manuals and User Guides for Fujitsu SPARC JPS1 Specification. We have 1 Fujitsu SPARC JPS1 Specification manual available for free PDF download: Implementation Supplement Manual

Fujitsu SPARC JPS1 Implementation Supplement Manual

Fujitsu SPARC JPS1 Implementation Supplement Manual (255 pages)

Fujitsu SPARC64 V

Brand: Fujitsu | Category: Computer Accessories | Size: 2 MB

Table of Contents

Table of Contents
4
1 Overview 1

12
- Overview
  12
- Navigating the SPARC64 V Implementation Supplement
  12
- Fonts and Notational Conventions
  12
- The SPARC64 V Processor
  13
  - Component Overview
    15
  - Instruction Control Unit (IU)
    17
  - Execution Unit (EU)
    17
  - Storage Unit (SU)
    18
  - Secondary Cache and External Access Unit (SXU)
    19
2 Definitions

20
3 Architectural Overview

24
4 Data Formats

26
5 Registers

28
- Nonprivileged Registers
  28
  - Floating-Point State Register (FSR)
    29
  - Tick (TICK) Register
    30
- Privileged Registers
  30
6 Instructions

36
- Instruction Execution
  36
  - Data Prefetch
    36
  - Instruction Prefetch
    37
  - Syncing Instructions
    38
- Instruction Formats and Fields
  39
- Instruction Categories
  40
- Processor Pipeline
  42
  - Instruction Fetch Stages
    42
  - Issue Stages
    44
  - Execution Stages
    44
  - Completion Stages
    45
7 Traps

46
- Processor States, Normal and Special Traps
  46
  - Error_State
    47
  - Red_State
    47
- Trap Categories
  48
  - Deferred Traps
    48
  - Reset Traps
    48
  - Uses of the Trap Categories
    48
- Trap Control
  49
  - PIL Control
    49
- Trap-Table Entry Addresses
  49
  - Trap Type (TT)
    49
  - Details of Supported Traps
    50
- Trap Processing
  50
- Exception and Interrupt Descriptions
  50
  - SPARC JPS1 Implementation-Dependent Traps
    50
  - SPARC V9 Implementation-Dependent, Optional Traps that Are Mandatory in SPARC JPS1
    50
8 Memory Models

52
- SPARC V9 Memory Model
  53
  - Mode Control
    53
  - Overview
    53
  - Synchronizing Instruction and Data Memory
    53
- Block Load and Store Instructions (VIS I)
  58
- Call and Link
  60
- Implementation-Dependent Instructions
  60
  - Floating-Point Multiply-Add/Subtract
    61
- Jump and Link
  64
- Load Quadword, Atomic [Physical]
  65
- Memory Barrier
  66
- Partial Store (VIS I)
  68
- Prefetch Data
  68
- Read State Register
  69
- Shutdown (Vis I)
  69
- Write State Register
  70
- Deprecated Instructions
  70
  - Store Barrier
    70
- Traps Inhibiting Results
  72
- Floating-Point Nonstandard Mode
  72
  - Operation under FSR.NS = 1
    76
- Definition of an Implementation Dependency
  80
- Hardware Characteristics
  81
- Implementation Dependency Categories
  81
- List of Implementation Dependencies
  81
E. Opcode Maps

94
- Virtual Address Translation
  96
- Translation Table Entry (TTE)
  97
  - TSB Organization
    99
  - TSB Pointer Formation
    99
- Faults and Traps
  100
- Reset, Disable, and Red_State Behavior
  102
- Internal Registers and ASI Operations
  103
- MMU Bypass
  115
  - TLB Replacement Policy
    116
- SPARC64 V ASI Assignments
  128
  - Special Memory Access Asis
    130
- Barrier Assist for Parallel Processing
  132
  - Interface Definition
    132
  - ASI Registers
    133
- Cache Types
  136
  - Level-1 Instruction Cache (L1I Cache)
    137
    
    Level-1 Data Cache (L1D Cache)
    138
    
    Level-2 Unified Cache (L2 Cache)
    138
  - Cache Coherency Protocols
    139
  - Cache Control/Status Instructions
    139
    
    Flush Level-1 Instruction Cache (ASI_FLUSH_L1I)
    140
    
    L2 Diagnostics Tag Read (ASI_L2_DIAG_TAG_READ)
    141
    
    Level-2 Cache Control Register (ASI_L2_CTRL)
    141
    
    L2 Diagnostics Tag Read Registers (ASI_L2_DIAG_TAG_READ_REG)
    142
  - Interrupt Dispatch
    144
  - Interrupt Receive
    146
  - Interrupt Global Registers
    147
  - Interrupt-Related ASR Registers
    147
    
    Interrupt Vector Dispatch Register
    147
    
    Interrupt Vector Dispatch Status Register
    147
    
    Interrupt Vector Receive Register
    147
  - Reset Types
    148
    
    Power-On Reset (POR)
    148
    
    Externally Initiated Reset (XIR)
    149
    
    Software-Initiated Reset (SIR)
    149
    
    Watchdog Reset (WDR)
    149
  - Red_State and Error_State
    150
    
    Error_State
    151
    
    Red_State
    151
    
    CPU Fatal Error State
    152
  - Processor State after Reset and in Red_State
    152
    
    Operating Status Register (OPSR)
    157
    
    Firmware Initialization Sequence
    158
    
    Hardware Power-On Reset Sequence
    158
  - Error Classification
    160
    
    Fatal Error
    160
  - Error_State Transition Error
    161
  - Urgent Error
    161
  - Restrainable Error
    163
- Action and Error Control
  164
- Fatal Error and Error_State Transition Error
  174
  - Asi_Stchg_Error_Info
    174
  - Fatal Error Types
    175
  - Types of Error_State Transition Errors
    175
- Urgent Error
  176
  - Urgent Error Status (Asi_Ugesr)
    176
- Instruction Access Errors
  184
- Data Access Errors
  184
- Restrainable Errors
  185
- Handling of Internal Register Errors
  192
- Cache Error Handling
  199
  - Handling of a Cache Tag Error
    199
  - Handling of an I1 Cache Data Error
    201
  - Handling of a D1 Cache Data Error
    201
  - Handling of a U2 Cache Data Error
    203
  - Automatic Way Reduction of I1 Cache, D1 Cache, and U2 Cache
    204
    
    Handling of TLB Entry Errors
    206
    
    TLB Error Handling
    206
    
    Automatic Way Reduction of Stlb
    207
    
    Handling of Extended UPA Address Bus Error
    208
    
    Handling of Extended UPA Bus Interface Error
    208
    
    Handling of Extended UPA Data Bus Error
    208
    
    Performance Monitor Overview
    212
    
    Sample Pseudocodes
    212
    
    Performance Monitor Description
    214
    
    Instruction Statistics
    215
    
    Trap-Related Statistics
    217
    
    MMU Event Counters
    218
    
    Cache Event Counters
    219
    
    UPA Event Counters
    221
    
    Miscellaneous Counters
    222
    
    Mapping of the Cpu's UPA Port Slave Area
    224
    
    UPA Portid Register
    225
    
    UPA Config Register
    226
- S. Summary of Differences between SPARC64 V and Ultrasparc-III
  
  230
- Bibliography
  
  234
  - General References
    234
- Index
  
  236

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