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A.30
Load Quadword, Atomic [Physical]
The Load Quadword ASIs in this section are specific to SPARC64 V, as an extension
to SPARC JPS1.
opcode
LDDA
LDDA
Format (3) LDDA
11
rd
11
rd
31
30 29
25
Assembly Language Syntax
ldda
ldda
Description
ASIs 34
data item, using physical addressing. The data are placed in an even/odd pair of 64-
bit registers. The lowest-address 64 bits are placed in the even-numbered register;
the highest-address 64 bits are placed in the odd-numbered register. The reference is
made from the nucleus context.
In addition to the usual traps for LDDA using a privileged ASI, a
data_access_exception
quadword-load ASIs with any instruction other than LDDA. A
mem_address_not_aligned
byte boundary.
ASIs 34
Quadword Atomic for virtually addressed data (ASIs 24
The memory access for a load quad instruction with ASI_QUAD_LDD_PHYS{_L}
behaves as if the following TTE is set:
54
SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
imm_asi
ASI_QUAD_LDD_PHYS
ASI_QUAD_LDD_PHYS_L
010011
010011
24
19 18
[reg_addr] imm_asi, reg
[reg_plus_imm]
and 3C
are used with the LDDA instruction to atomically read a 128-bit
16
16
exception occurs for a noncacheable access or for the use of the
exception is generated if the access is not aligned on a 16-
and 3C
are supported in SPARC64 V in addition to those for Load
16
16
ASI value
34
16
3C
16
rs1
i=0
imm_asi
rs1
i=1
14 13
rd
, reg
%asi
rd
operation
128-bit atomic load, physically
addressed
128-bit atomic load, little-endian,
physically addressed
simm_13
5
4
and 2C
).
16
16
rs2
0
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