Table of Contents
Advertisement
b. Write the U2 cache line with the
c. Clear ASI_AFSR.CE_INCOMED and reload the memory block to U2 cache,
d. If the
ASI_AFSR.UE_DST_BETO
This error is always caused by a mistake in privileged software. Record the error
and correct the erroneous privileged software.
ASI_AFSR.UE_RAW_L2$FILL
handles these errors as follows:
No error indication in ASI_AFSR at
This situation may occur at the condition described in the
(see the third row, last column, and "Deviation from the ideal specification").
180
SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
ASI_L2_CTRL.U2_FLUSH facility or by displacement flush.
using load instructions. Check whether the CE in memory has been corrected
by inspecting ASI_AFSR.CE_INCOMED and ASI_AFAR_U2.
in memory block is not corrected, a permanent error may be detected.
CE
Avoid using the memory block with the permanent correctable error as much
as possible.
— This error is caused by either:
Invalid DTLB entry is specified, or
Invalid memory access instruction with physical address access ASI is executed
in privileged software.
Correct the cache line data containing the uncorrected error by executing a
block store with commit instruction, if possible. Note that the original data is
deleted by this operation.
For UE_RAW_L2$FILL, avoid using the memory block with the
possible.
detection to memory either by using the
CE
,
, and
UE_RAW_L2$INSD
trap — Ignore the
ECC_error
— Software
UE_RAW_D1$INSD
as much as
UE
ECC_error
on page 154
TABLE P-2
trap.
Advertisement
Table of Contents
