Fujitsu SPARC JPS1 Implementation Supplement Manual page 154

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ASR State after Reset and in RED_state
TABLE O-2
A
S
R
Name
0
Y
2
CCR
3
ASI
4
TICK
NPT
Counter
6
FSR
16
PCR
UT
ST
Others
17
PIC
18
DCR
19
GSR
IM
STE
O
thers
22
SOFTINT
23
TICK_COMPARE
INT_DIS
TICK_CMPR
24
STICK
NPT
Counter
25
STICK_COMPARE
INT_DIS
TICK_CMPR
1.Hard POR occurs when power is cycled. Values are unknown following hard POR. Soft POR occurs when
UPA_RESET_L is asserted. Values are unchanged following soft POR.
2.The first watchdog timeout trap is taken in execute_state (i.e. PSTATE.RED = 0), subsequent watchdog timeout
traps as well as watchdog traps due to a trap @ TL = MAX_TL are taken in RED_state. See Section O.1.2, Watchdog
Reset (WDR), on page 138or more details
ASI Register State After Reset and in
TABLE O-3
A
S
I
VA
Name
45
00
DCUCR
45
08
MCNTL
48
00
INST_BREAKPOINT
49
00
INTR_RECEIVE
Release 1.0, 1 July 2002
1
POR
WDR
Unknown/Unchanged
Unchanged
Unknown/Unchanged
Unchanged
Unknown/Unchanged
Unchanged
1
Unchanged
Restart at 0
Unchanged
0
Unchanged
0
Unchanged
0
Unknown/Unchanged
Unknown/Unchanged
Unchanged
Always 0
0
Unchanged
0
Unchanged
Unknown/Unchanged
Unchanged
Unknown/Unchanged
Unchanged
1
Unchanged
0
Unchanged
1
Unchanged
Restart at 0
Unchanged (count)
1
Unchanged
0
Unchanged
RED_state
1
POR
0
0
0 (off)
Unknown/Unchanged
2
XIR
Unchanged
Restart at 0
(1 of 3)
2
WDR
0
0
Unchanged
Unchanged
F. Chapter O
Reset, RED_state, and error_state
RED_state
SIR
Unchanged
Unchanged
XIR
SIR
RED_state
143

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