Component Overview - Fujitsu SPARC JPS1 Implementation Supplement Manual

Asynchronous data error (
1.3.1

Component Overview

The SPARC64 V processor contains these components.
Instruction control Unit (IU)
Execution Unit (EU)
Storage Unit (SU)
Secondary cache and eXternal access Unit (SXU)
FIGURE 1-1
4 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
Relaxed instruction end method (precise, retryable, not retryable) for the
exception to indicate how the instruction should end; depends
async_data_error
on the executing instruction and the detected error.
Some traps that are deferred but retryable.
ADE
Simultaneous reporting of all detected
handling of retryability.
illustrates the major units; the following subsections describe them.
) trap for additional errors:
ADE
errors at the error barrier for correct
ADE