Mmu Bypass - Fujitsu SPARC JPS1 Implementation Supplement Manual

Fujitsu sparc64 v
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DSFSR
TABLE F-10
Field
Miss on fault/exception
Miss on miss
1.
The value of DSFSR.CT is 11 when the ASI is not a translating ASI. The value 11 is recorded in DSFSR.CT for
an illegal value in ASI (00
2.
Valid only for the
3.
Types: 0 – logic 0; 1 – logic 1; V – Valid field to be updated; "—" – not a valid field
4.
Memory reference instruction only.
5.
Updated when mDTLB is signified.
6.
Types: 0 – logic 0; 1 – logic 1; V– Valid field to be updated; "—" – not a valid field
7.
Fault/exception on miss means the miss happened first, then a fault/exception was encountered before soft-
ware had a chance to clear the DSFSR register.
F.11

MMU Bypass

On SPARC64 V, two additional ASIs are supported as DMMU bypass accesses:
ASI_ATOMIC_QUAD_LDD_PHYS (ASI 34
ASI_ATOMIC_QUAD_LDD_PHYS_LITTLE (ASI 3C
TABLE F-11
conform to the bypass attribute bits defined in
Bypass Attribute Bits
TABLE F-11
ASI
NAME
ASI_PHYS_USE_EC
ASI_PHYS_USE_EC_LITTLE
ASI_PHYS_BYPASS_EC_WITH_EBIT
ASI_PHYS_BYPASS_EC_WITH_EBIT_LITTLE
ASI_ATOMIC_QUAD_LDD_PHYS
ASI_ATOMIC_QUAD_LDD_PHYS_LITTLE
104
SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
TLB#,
FV
index
K
K
K
–03
, 12
–13
, 16
16
16
16
16
caused by DSFSR.UE or DSFSR.UPA.
data_access_error
shows the bypass attribute bits on SPARC64 V. The first four rows
on SPARC64 V
W, PR,
OW
FT
1
NF, CT
1
K
K
K
K
U
K
–17
, 1A
–1B
, 1E
16
16
16
16
16
) and
16
ASI
VALUE CP
IE
CV
14
1
0
0
16
1C
16
15
0
0
0
16
1D
16
34
0
0
1
16
3C
16
UE, UPA,
TM
ASI
mDTLB, NC
1
K
K
1
K
K
–23
, 2D
–2F
, or 35
16
16
16
16
)
16
F-15 of Commonality.
TABLE
Attribute Bits
E
P
W
0
0
1
1
0
1
0
0
0
DSFAR
2
2
, E
K
K
–3B
).
16
NFO
Size
0
8 Kbytes
0
8 Kbytes
0
8 Kbytes

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