Cache Error Handling; Handling Of A Cache Tag Error - Fujitsu SPARC JPS1 Implementation Supplement Manual

SPARC64 V Implementation and the Ideal Specification
In the table on page 183 (defining terminology in
7F , and EF
16
indicate that the SPARC64 V implementation deviates from the ideal specification,
which is described in
Ideal Handling of ASI Register Errors (not implemented in SPARC64 V)
TABLE P-21
ASI VA
Register name
6F — Parallel barrier assist
16
7F 40 -88
INTR_DATA0:7_R
16 16 16
EF — Parallel barrier assist
16
P.9

Cache Error Handling

In this section, handling of cache errors of the following types is specified:
Cache tag errors
Cache data errors in I1, D1, and U2 caches
This section concludes with the specification of automatic way reduction in the I1,
D1, and U2 caches.
P.9.1

Handling of a Cache Tag Error

Error in D1 Cache Tag and I1 Cache Tag
Both the D1 cache (Data level 1) and the I1 cache (Instruction level 1) maintain a
copy of their cache tags in the U2 (unified level 2) cache. The D1 cache tags, the D1
cache tags copy, the I1 cache tags, and the I1 cache tags copy are each protected by
parity.
188 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
) with error type of "Not detected (#dv)" or "
16
but is not implemented in SPARC64 V.
TABLE P-21
Error
RW Protect
RW Parity
R ECC
RW Parity
TABLE P-20
Error Detect
Condition Error Type
always (I)AUG_CRE
AUG
I(A)UG_CRE
LDXA
(I)AUG_CRE
BV interface
I(A)UG_CRE
LDXA
is set to 0
BUSY
intr_receive
always (I)AUG_CRE
AUG
I(A)UG_CRE
LDXA
(I)AUG_CRE
BV interface
), the rows (ASIs 6F
16
(#dv)"
COREERROR
Correction
W
W
None
Interrupt
Receive
W
W
None
,