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1. The opcode of the instructions should be ldda, ldxa, lddfa, stda, stxa, or
stdfa. Otherwise, a
(Invalid ASI) is generated.
2. No operand address translation is performed for these instructions.
3. VA<2:0> of all of the operand address should be 0. Otherwise, a
mem_address_not_aligned
4. The don't-care bits (designated "—" in the format) in the VA of the load or store
alternate can be of any value. It is recommended that software use zero for these
bits in the operand address of the instruction.
5. The don't-care bits (designated "—" in the format) in DATA are read as zero and
ignored on write.
6. The instruction operations are not affected by PSTATE.CLE. They are always
treated as big-endian.
7. The instructions are all strongly ordered regardless of load or store and the
memory model. Therefore, no speculative executions are performed.
Multiple Asynchronous Fault Address Registers are maintained in hardware, one for
each major source of asynchronous errors. These ASIs are described in
ASI_ASYNC_FAULT_STATUS (ASI_AFSR) on page 174. The following subsections
describe all other cache-related ASIs in detail.
M.3.1
Flush Level-1 Instruction Cache
(ASI_FLUSH_L1I)
[1]
[2]
[3]
[4]
ASI_FLUSH_L1I flushes and invalidates the entire level-1 instruction cache. VA can
be any value. A write to this ASI with any VA and any data causes flushing and
invalidation.
Release 1.0, 1 July 2002
data_access_exception
exception is generated.
Register Name:
ASI:
VA:
RW
exception with D-SFSR.FT = 08
ASI_FLUSH_L1I
67
16
Any
Supervisor write
F. Chapter M
16
Cache Organization
129
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