Operating Status Register (Opsr) - Fujitsu SPARC JPS1 Implementation Supplement Manual

UPA slave register State after Reset and in RED_state
TABLE O-4
PA Name
00
UPA_PORTID
Cookie
SREQ_S
ECCnotValid
One_Read
PRINT_RDQ
PREQ_DQ
PREQ_RQ
UPACAP
1.Hard POR occurs when power is cycled. Values are unknown following hard POR. Soft POR occurs when
UPA_RESET_L is asserted. Values are unchanged following soft POR.
2.The first watchdog timeout trap is taken in execute_state (i.e. PSTATE.RED = 0), subsequent watchdog timeout
traps as well as watchdog traps due to a trap @ TL = MAX_TL are taken in RED_state. See Section O.1.2, Watch-
dog Reset (WDR), on page 138 for more details.
O.3.1

Operating Status Register (OPSR)

OPSR is the control register in the CPU that is scanned in during the hardware
power-on reset sequence before the CPU starts running.
The value of the OPSR is specified outside of the CPU and is never changed by
software. OPSR is set by scan-in during hardware power-on reset and by a JTAG
command after hardware POR.
Most of OPSR setting is not visible for software. However, some OPSR values control
the software-visible action.
The following items are controlled by OPSR and are visible to software.
1. Initial value of the physical address mode.
The hardware POR initial value of the 41-bit PA mode or 43-bit PA mode is
specified by OPSR and set in UPA_CONFIG.AM field. In 41-bit PA mode, all
physical addresses issued by the CPU are masked to 41 bits. Otherwise, the CPU
operates in 43-bit PA mode, and physical addresses issued by CPU are masked to
43 bits.
2. The value of UPA_configuration_register.MCAP field.
OPSR can be set so that when error_state is entered, the processor remains
halted in error_state instead of generating a
146 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
1
POR (binary)
FC
16
1
0
0
01
000000
0001
11011
2
WDR XIR
Unchanged
Unchanged
Unchanged
Unchanged
Unchanged
Unchanged
Unchanged
Unchanged
watchdog_reset
RED_state
SIR
(impl. dep. #254).