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O.2.3
CPU Fatal Error state
The processor enters CPU fatal error state when a fatal error is detected on the
processor. A fatal error is one that breaks the cache coherency or the system data
integrity and is not reported as the SDC (small data corruption) error. See Appendix
P, Error Handling, for details of the SDC error.
The processor reports the fatal error detection to the system, and the system causes
the fatal reset. Soft POR will be applied to the all CPUs in the system at the fatal
reset.
O.3
Processor State after Reset and in
RED_state
TABLE O-1
RED_state.
In this table, it is assumed that RED_state entry happens as a result of resets or
traps. If RED_state entry occurs because the WRPR instruction sets the PSTATE.RED
bit, no processor state will be changed except the PSTATE.RED bit itself; the effects
of this are described in RED_state on page 140.
Nonprivileged and Privileged Register State after Reset and in
TABLE O-1
Name
Integer registers
Floating Point registers
value
RSTV
PC
nPC
PSTATE
AG
MG
IG
IE
PRIV
AM
PEF
RED
MM
Release 1.0, 1 July 2002
shows the various processor states after resets and when entering
1
POR
Unknown/Unchanged
Unknown/Unchanged
VA =
FFFF FFFFF000 0000
PA =
16 (43-bit PA mode specified by
07FF F000 0000
|
20
RSTV
16
|
4
2
RSTV
16
1 (Alternate globals)
0 (MMU globals not selected)
0 (Interrupt globals not selected)
0 (Interrupt disable)
1 (Privileged mode)
0 (Full 64-bit address)
1 (FPU on)
1 (Red_state)
00 (TSO)
2
WDR
XIR
Unchanged
Unchanged
16
|
|
40
60
RSTV
RSTV
16
|
|
44
64
RSTV
RSTV
16
F. Chapter O
Reset, RED_state, and error_state
RED_state
SIR
RED_state
)
OPSR.
|
80
RSTV
RSTV
16
16
|
84
RSTV
RSTV
16
16
|
A0
16
|
A4
16
141
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