Fujitsu SPARC JPS1 Implementation Supplement Manual page 186

ASI_ASYNC_FAULT_STATUS
TABLE P-15
Bit Name
Bits 10:0 are restrainable error-pending "sticky" bits. Each bit in
corresponding error is detected. The only way each of these error sticky bits can be cleared is to write 1 to it.
When 1 is held in a bit of
an ECC_error trap is generated.
10
DG_L1$U2$STLB
9
CE_INCOMED
Release 1.0, 1 July 2002
If the column for the error shown in the table row is blank, the error is
Prio_U2
never recorded into ASI_AFAR_U2.
Otherwise, the
Prio_U2
the ASI_AFAR_U2 recording priority, as follows. Let P_U2 be the
column value for the error
Upon detection of the error
is recorded into ASI_AFAR_U2 and ASI_AFAR_U2.CONTENTS is set
E2
to P_U2.
Upon detection of the error
is not recorded in ASI_AFAR_U2 and ASI_AFAR_U2 is unchanged.
E2
Bit Description
R/W Prio_D1 Prio_U2
ASI_AFSR and the trap disable condition specified in the
RW1C
RW1C
column for the error shown in the table row indicates
. Then:
E2
, if P_U2 > ASI_AFAR_U2.CONTENTS, the error
E2
, if P_U2 ASI_AFAR_U2.CONTENTS, the error
E2
Description
ASI_AFSR
Degradation in L1$, U2$, and sTLB. This bit is set
when automatic way reduction is applied in I1$,
D1$, U2$, sITLB, or sDTLB. See Section P.9.5 and
Section P.10.2 for further details about when this bit
is set.
40 Correctable error in incoming data from the UPA bus.
16
is detected in the following cases:
CE
• U2 (unified level 2) cache fill
• Data read from noncacheable area
The two cases can be separated by the physical
address indicated in ASI_AFAR_U2. For U2 cache fill,
normally the
CE
Programming Note: Data is transferred on the UPA
bus in units of 16 bytes (one quadword). For data
read from a noncacheable area, a correctable error in
the opposite doubleword from the one that was
accessed by the instruction may be reported as
.
CE_INCOMED
The address indicated in ASI_AFAR_U2 for
always has doubleword resolution and
CE_INCOMED
indicates the correct error location for the incoming
data path. However, the error reported for the
noncacheable area read may be for the opposite
doubleword in a quadword from the doubleword
accessed by the instruction.
Prio_U2
<10:0> is set to 1 when the
TABLE P-2 is not satisfied,
in DIMM is detected.
F. Chapter P Error Handling 175