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Events and Encoding of Performance Monitor (Continued)
TABLE Q-1
Counter
Encoding
picu0
picl0
001101
Reserved
001110
Reserved
001111
Reserved
010000
Reserved
010001
Reserved
010010
Reserved
010011
Reserved
010100
Reserved
010101
Reserved
010110
trap_all
trap_int_vector trap_int_level trap_spill
010111
Reserved
100000
Reserved
100001
Reserved
100010
Reserved
100011
Reserved
110000
sx_miss
sx_miss_wait
_pf
_wait_dm
110001
sreq_bi
sreq_cpi_count sreq_cpb
_count
110010
Reserved
110011
Reserved
111111
Disabled
Q.2.1
Instruction Statistics
Instruction statistics counters can be monitored by any SU or SL of any PIC.
204
SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
picu1
write_if_uTLB write_op_uTLB if_r_iu_req_mi
sx_miss_count
sx_miss_count_
_dm
pf
sreq_cpd_count upa_abus_busy upa_data_busy asi_rd_bar
_count
Performance Monitor Cycle Count (cycle_counts)
Counter
Any
Encoding
000000
Counts the cycles when the performance monitor is enabled. This counter is
similar to the %tick register but can separate user cycles from system cycles,
based on PCR.UT and PCR.ST selection.
picl1
picu2
trap_fill
_go
sx_read_count
_dm
2
picl2
picu3
trap_trap_inst trap_IMMU
_miss
op_r_iu_req
if_wait_all
_mi_go
sx_read_count
dvp_count_dm dvp_count_pf
_pf
picl3
trap_DMMU
_miss
op_wait_all
asi_wr_bar
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