Action And Error Control; Registers Related To Error Handling - Fujitsu SPARC JPS1 Implementation Supplement Manual

Fujitsu sparc64 v
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Degradation
SPARC64 V can isolate an internal hardware resource that generates frequent
errors and continue processing without deleterious effect on software during
program execution. However, performance is degraded by the resource isolation.
This degradation is reported as a restrainable error.
The restrainable error can be reported to privileged software by the
When PSTATE.IE = 1 and the trap enable mask for any restrainable error is 1, the
ECC_error
P.2

Action and Error Control

P.2.1

Registers Related to Error Handling

The following registers are related to the error handling.
ASI registers: Indicate an error. All ASI registers in
and ASI_ERROR_CONTROL are used to specify the nature of an error to privileged
software.
ASI_ERROR_CONTROL: Controls error action. This register designates error
detection masks and error trap enable masks.
ASI_EIDR: Marks errors. This register identifies the error source ID for error
marking.
TABLE P-1
Registers Related to Error Handling
TABLE P-1
ASI
VA
R/W
4C
00
RW1C
16
16
4C
08
R
16
16
4C
10
RW
16
16
4C
18
R,W1AC
16
16
4D
00
RW1AC
16
16
4D
08
RW1AC
16
16
50
18
RW
16
16
58
18
RW
16
16
58
20
RW
16
16
6E
00
RW
16
16
Release 1.0, 1 July 2002
exception is generated for the restrainable error.
lists the registers related to error handling.
Checking Code
Name
None
ASI_ASYNC_FAULT_STATUS
None
ASI_URGENT_ERROR_STATUS
Parity
ASI_ERROR_CONTROL
None
ASI_STCHG_ERROR_INFO
Parity
ASI_ASYNC_FAULT_ADDR_D1
Parity
ASI_ASYNC_FAULT_ADDR_U2
None
ASI_IMMU_SFSR
None
ASI_DMMU_SFSR
Parity
ASI_DMMU_SFAR
Parity
ASI_EIDR
ECC_error
except ASI_EIDR
TABLE P-1
Defined in
P.7.1
P.4.1
P.2.1
P.3.1
P.7.2
P.7.3
F.10.9
F.10.9
F.10.10 of Commonality
P.2.5
F. Chapter P
Error Handling
trap.
153

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