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ASI_UGESR
TABLE P-11
Bit
Name
5:4
INSTEND
3
PRIV
2
MUGE_DAE
1
MUGE_IAE
0
MUGE_IUGE
Other
Reserved
P.4.2
Action of async_data_error (
The single-
defined in
more detail in this section. For convenience, the shorthand
async_data_error
1. Conditions that cause
An
2. State change, trap target address calculation, and TL manipulation.
168
SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
Bit Description (4 of 4)
RW
Description
R
Trapped instruction end-method. Upon a single async_data_error trap
without watchdog timeout detection, INSTEND indicates the instruction end-
method of the trapped instruction pointed to by TPC as follows:
00
: Precise
2
01
: Retryable but not precise
2
10
: Reserved
2
11
: Not retryable
2
See Section P.4.3 for the instruction end-method for the async_data_error trap.
When a watchdog timeout is detected, the instruction end-method is
undefined.
R
Privileged mode. Upon a single async_data_error trap, the PRIV field is set as
follows:
When the value of PSTATE.PRIV immediately before the single-
unknown because of an uncorrectable error in PSTATE, ASI_UGESR.PRIV is
set to 1. Otherwise, the value of PSTATE.PRIV immediately before the single-
trap is copied to ASI_UGESR.PRIV.
ADE
R
Multiple
s caused by
UGE
a multiple-
ADE
trap not caused by a
ADE
R
Multiple
s caused by
UGE
Upon a multiple-
multiple-
trap not caused by an
ADE
R
Multiple
s caused by
UGE
0. Upon a multiple-
a multiple-
ADE
R
Always 0.
trap and the multiple-
ADE
on page 154. The actions upon their occurrence are defined in
TABLE P-2
.
ADE
trap occurs when one of the following conditions is satisfied:
ADE
When ASI_ERROR_CONTROL.UGE_HANDLER = 0 and
detected, a single-
ADE
When ASI_ERROR_CONTROL.UGE_HANDLER = 1 and
are detected, a multiple-
. Upon a single-
DAE
trap caused by a
, MUGE_DAE is set to 1. Upon a multiple-
DAE
,
DAE
MUGE_DAE
. Upon a single-
IAE
trap caused by an
ADE
IAE
. Upon a single-
I_UGE
trap caused by an
ADE
trap not caused by an
I_UGE
ADE
trap are generated upon the conditions
ADE
trap:
trap is generated.
trap is generated.
ADE
MUGE_DAE is set to 0. Upon
ADE,
is unchanged.
trap, MUGE_IAE is set to 0.
ADE
, MUGE_IAE is set to 1. Upon a
IAE
,
is unchanged.
MUGE_IAE
trap, MUGE_IUGE is set to
ADE
MUGE_IUGE is set to 1. Upon
I_UGE,
,
is unchanged.
MUGE_IUGE
) Trap
is used to refer to
ADE
s and/or
I_UGE
,
, and/or
I_UGEs
IAE
trap is
ADE
s are
A_UGE
DAE
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