Fujitsu SPARC JPS1 Implementation Supplement Manual page 77

summarizes the behavior of SPARC64 V floating-point hardware depending on
FSR.NS.
Note – The result and behavior of SPARC64 V of the shaded column in the tables
Table B-5 and Table B-6 conform to IEEE754-1985 standard.
Note – Throughout Table B-5 and Table B-6, lowercase exception conditions such as
nx, uf, of, dv and nv are nontrapping IEEE 754 exceptions. Uppercase exception
conditions such as NX, UF, OF, DZ and NV are trapping IEEE 754 exceptions.
Floating-Point Exceptional Conditions and Results
TABLE B-5
FSR.N Denorm : Result
1
S Norm Denorm
No Yes
0
No
Yes n/a
No Yes
1
No
Yes —
1. One of the operands is a denormalized number, and the other operand is a normal or a denormalized number
(non- zero, non-NaN, and non-infinity).
2. The result before rounding turns out to be a denormalized number.
3. Dmin = denormalized minimum.
4. If the FPop is either FADD{s,d}, or FSUB{s,d} and the operation is 0 ± denormalized number, SPARC64 V does
not generate an unfinished_FPop and generates a result according to IEEE754-1985 standard.
5. Nmax = normalized maximum.
66 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
Pessimistic Pessimistic
2
Zero Overflow
Yes
—
No
— —
Yes —
No Yes
No
— —
UFM OFM NXM
1 — —
0 — 1
— 0
1 — —
0 — —
— — —
1 —
—
0 1
0
1 —
—
0 1
0
— —
1 — —
0 — 1
0
— — —
Result
UF
NX
uf + nx, a signed zero, or a signed
3
Dmin
UF
4
unfinished_FPop
Conforms to IEEE754-1985
UF
NX
uf + nx, a signed zero, or a signed
Dmin
OF
NX
of + nx, a signed infinity, or a
5
signed Nmax
unfinished_FPop
UF
NX
uf + nx, a signed zero
Conforms to IEEE754-1985
TABLE B-6