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N
F. A P P E N D I X
Interrupt Handling
Interrupt handling in SPARC64 V is described in these sections:
Interrupt Dispatch on page 133
Interrupt Receive on page 135
Interrupt-Related ASR Registers on page 136
N.1
Interrupt Dispatch
When a processor wants to dispatch an interrupt to another UPA port, it first sets up
the interrupt data registers (ASI_INTR_W data 0-7) with the outgoing interrupt
packet data by using ASI instructions. It then performs an ASI_INTR_W (interrupt
dispatch) write to trigger delivery of the interrupt. The interrupt packet and the
associated data are forwarded to the target UPA by the system controller. The
processor polls the BUSY bit in the INTR_DISPATCH_STATUS register to determine
whether the interrupt has been dispatched successfully.
FIGURE N-1
illustrates the steps required to dispatch an interrupt.
133
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