Handling Of Internal Register Errors; Register Error Handling (Excluding Asrs And Asi Registers) - Fujitsu SPARC JPS1 Implementation Supplement Manual

P.8

Handling of Internal Register Errors

This section describes error handling for the following:
Most registers
ASR registers
ASI registers
P.8.1 Register Error Handling (Excluding ASRs and ASI
Registers)
The terminology used in
Column
Error Detect
Condition
Correction
TABLE P-18
TABLE P-18
Register Name
%rn
%fn
PC
nPC
PSTATE
TBA
PIL
CWP, CANSAVE,
CANRESTORE,
OTHERWIN,
CLEANWIN
TT
TL
Release 1.0, 1 July 2002
TABLE P-18
Term Meaning
InstAccess The error is detected when the instruction accesses the register.
W The error indication is removed when an instruction performs a
full write to the register
trap The error is removed by a full write to the register in the
ADE
async_data_error
shows error handling for most registers.

Register Error Handling (Excluding ASRs and ASI Registers)

Error
RW Protect
RW Parity
RW Parity
Parity
Parity
RW Parity
RW Parity
RW Parity
RW Parity
RW None
RW Parity
is defined as follows:
hardware trap sequence.
Error Detect Condition Error Type
InstAccess IUG_%R
InstAccess IUG_%F
Always IUG_PSTATE
Always IUG_PSTATE
Always IUG_PSTATE
PSTATE.RED = 0
error_state
PSTATE.IE = 1 IUG_PSTATE
or InstAccess
Always IUG_PSTATE
— —
PSTATE.RED = 0
error_state
F. Chapter P
Correction
W
W
trap
ADE
trap
ADE
trap
ADE
W (by )
OBP
W
trap, W
ADE
—
W (by )
OBP
Error Handling 181