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TABLE C-1
Nbr
42
43
44
45–46
47
48
49–54
55
56–100 Reserved.
101
102
103
104
105
Release 1.0, 1 July 2002
SPARC64 V Implementation Dependencies (4 of 11)
SPARC64 V Implementation Notes
FLUSH instruction
SPARC64 V
implements the FLUSH instruction in hardware.
Reserved.
Data access FPU trap
The destination register(s) are unchanged if an access error occurs.
Reserved.
RDASR
See A.50, Read State Register, in Commonality for details.
WRASR
See A.70, Write State Register, in Commonality for details.
Reserved.
Floating-point underflow detection
See
in Section 5.1.7 of Commonality for details.
FSR_underflow
Maximum trap level
MAXTL = 5.
Clean windows trap
SPARC64 V
generates a
cleaned in software.
Prefetch instructions
SPARC64 V
implements PREFETCH variations 0–3 and 20–23 with the
following implementation-dependent characteristics:
• The prefetches have observable effects in privileged code.
• Prefetch variants 0–3 do not cause a
because the prefetch is dropped when a
condition happens. On the other hand, prefetch variants 20–23 cause
data_access_MMU_miss
• All prefetches are for 64-byte cache lines, which are aligned on a 64-byte
boundary.
• See Section A.49, Prefetch Data, on page 57, for implemented variations
and their characteristics.
• Prefetches will work normally if the ASI is ASI_PRIMARY,
ASI_SECONDARY, or ASI_NUCLEUS, ASI_PRIMARY_AS_IF_USER,
ASI_SECONDARY_AS_IF_USER, and their little-endian pairs.
VER.manuf
VER.manuf = 0004
. The least significant 8 bits are Fujitsu's JEDEC
16
manufacturing code.
TICK register
SPARC64 V
implements 63 bits of the TICK register; it increments on every
clock cycle.
exception; register windows are
clean_window
fast_data_access_MMU_miss
fast_data_access_MMU_miss
traps on TLB misses.
F. Chapter C
trap,
Implementation Dependencies
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