Fujitsu SPARC JPS1 Implementation Supplement Manual page 181

b. Update of ASI_UGESR, as shown in
ASI_UGESR
TABLE P-13
Bit Field
63:6 Error indication All bits in this field are updated.
5:4
INSTEND
2
MUGE_DAE[
1
MUGE_IAE
0
MUGE_IUGE
c. Update of ASI_ERROR_CONTROL
4. Set ASI_ERROR_CONTROL.UGE_HANDLER to 0.
Upon completion of a RETRY or DONE instruction,
ASI_ERROR_CONTROL.UGE_HANDLER is set to 0.
P.4.3 Instruction End-Method at
In SPARC64 V, upon occurrence of the
by TPC ends by using one of the following instruction end-methods:
Precise
Retryable but not precise (not included in JPS1)
Not retryable (not included in JPS1)
Upon a single-ADE trap, the trapped instruction end-method is indicated in
ASI_UGESR.INSTEND.
170 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
Errors in registers other than those listed above and any errors in the TLB entry
remain.
Update for Single and Multiple-
Update upon a Single-ADE Trap
All s and
I_UGE A_UGE
trap are indicated simultaneously.
The instruction end-method of the
instruction referenced by TPC is set.
Set to 0.
Set to 0.
Set to 0.
Upon a single- trap, ASI_ERROR_CONTROL.UGE_HANDLER is set to 1.
ADE
During the period after the single-
instruction is executed, UGE_HANDLER = 1 tells hardware that the urgent error
handler is running.
Upon a multiple
async_data_error
to 1 and the CPU starts running in the weak error detection state.
TABLE P-13
Exceptions
ADE
Update upon a Multiple-ADE Traps
Unchanged.
s detected at the
Unchanged.
If the multiple-
,
DAE
Otherwise,
If the multiple-
an
IAE
Otherwise,
If the multiple-
an
I_UGE
Otherwise,
trap occurs and before a RETRY or DONE
ADE
trap, ASI_ERROR_CONTROL.WEAK_ED is set
ADE
trap, the trapped instruction referenced
ADE
.
trap was caused by a
ADE
is set to 1.
MUGE_DAE
is unchanged.
MUGE_DAE
trap was caused by
ADE
, is set to 1.
MUGE_IAE
is unchanged.
MUGE_IAE
trap was caused by
ADE
, is set to 1.
MUGE_IUGE
is unchanged.
MUGE_IUGE
Trap