Issue Stages; Execution Stages - Fujitsu SPARC JPS1 Implementation Supplement Manual

Fujitsu sparc64 v

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6.4.2

Issue Stages

E (Entry) — Instructions are passed from fetch stages.

D (Decode) — Assign resources and dispatch to reservation station (RS.)

SPARC64 V is an out-of-order execution CPU. It has six execution units (two of

arithmetic and logic unit, two of floating-point unit, two of load/store unit). Each

unit except the load/store unit has its own reservation station. E and D stages are

issue stages that decode instructions and dispatch them to the target RS. SPARC64 V

can issue up to four instructions per cycle.

The resources needed to execute an instruction are assigned in the issue stages. The

resources to be allocated include the following:

Resources needed for an instruction are specific to the instruction, but all resources

must be assigned at these stages. In normal execution, assigned resources are

released at the very last stage of the pipeline, W-stage.

stage and W-stage are considered to be in-flight. When an exception is signalled, all

in-flight instructions and the resources used by them are released immediately. This

behavior enables the decoder to restart issuing instructions as quickly as possible.

The number of in-flight instructions depends on how many resources are needed by

them. The maximum number is 64.

6.4.3

P (priority) — Select an instruction from those that have met the conditions for

execution.

B (buffer read) — Read register file, or receive forwarded data from another

pipelines.

X (execute) — Execution.

Instructions in reservation stations will be executed when certain conditions are met,

for example, the values of source registers are known, the execution unit is available.

Execution latency varies from one to many, depending on the instruction.

1. An entry in a reservation station is released at the X-stage.

Release 1.0, 1 July 2002

Commit stack entry (CSE)

Renaming registers of integer (GUB) and floating-point (FUB)

Entries of reservations stations

Memory access ports

Instructions between the E-

F. Chapter 6

Instructions

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