S. Summary Of Differences Between Sparc64 V And Ultrasparc-Iii - Fujitsu SPARC JPS1 Implementation Supplement Manual

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F. A P P E N D I X
Summary of Differences between
SPARC64 V and UltraSPARC-III
The following table summarizes differences between SPARC64 V and UltraSPARC-III
ISAs. This list is a summary, not an exhaustive list.
SPARC64 V and UltraSPARC-III Differences
TABLE T-1
Feature SPARC64 V
MMU SPARC64 V supports an
architecture UltraSPARC II-based MMU model.
TLBs are split between instruction
and data. Each side has a 2-level
TLB hierarchy.
TTE format SPARC64 V supports a 43-bit
physical address. In addition, the
CV bit is ignored and unaliasing is
maintained by hardware.
TLB locking Lock entries are supported in both
mechanism fully-associative ITLB (fITLB) and
fully-associative DTLB (fDTLB), 32-
entry each.
TSB hashing Direct hashing with contents of the
algorithm Context-ID register (13-bit). Has a
UltraSPARC I/II compatibility
mode.
Floating-point SPARC64 V implements these
Multiply-ADD instructions in IMPDEP2.
(1 of 3)
SPARC64 V
Page UltraSPARC-III
85 UltraSPARC-III implements a flat
extended version of UltraSPARC
II's MMU architecture.
86 UltraSPARC-III supports a 43-bit
physical address. Millennium
will support a 47-bit PA.
86 Lock entries supported only in
the 16-entry fully-associative
TLBs.
88 Hash field in pointer extension is
used for hashing address. Setting
0 in the field maintains
compatibility with UltraSPARC
I/II.
50 Does not support FMA
instructions.
UltraSPARC-
III Section
F-1
F-2
F-1, F-2
F. 10.7
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