Fujitsu SPARC JPS1 Implementation Supplement Manual page 129

SPARC64 V ASI Assignments (2 of 3)
TABLE L-1
Value ASI Name (Suggested Macro Syntax)
45 ASI_DCU_CONTROL_REG (ASI_DCUCR)
16
45
ASI_MEMORY_CONTROL_REG
16
46 –49 (JPS1)
16 16
4A
ASI_UPA_CONFIG_REGISTER
16
4B (JPS1)
16
4C
ASI_ASYNC_FAULT_STATUS
16
4C
ASI_URGENT_ERROR_STATUS
16
(ASI_UGESR)
4C
ASI_ERROR_CONTROL
16
4C
ASI_STCHG_ERROR_INFO
16
4D
ASI_ASYNC_FAULT_ADDR_D1
16
4D
ASI_ASYNC_FAULT_ADDR_U2
16
4E (JPS1)
16
4F
ASI_SCRATCH_REG0
16
4F
ASI_SCRATCH_REG1
16
4F
ASI_SCRATCH_REG2
16
4F
ASI_SCRATCH_REG3
16
4F
ASI_SCRATCH_REG4
16
4F
ASI_SCRATCH_REG5
16
4F
ASI_SCRATCH_REG6
16
4F
ASI_SCRATCH_REG7
16
50 –66
(JPS1)
16 16
67
ASI_ALL_FLUSH_L1I
16
68 –69
(JPS1)
16 16
6A
ASI_L2_CTRL
16
6B
ASI_L2_DIAG_TAG_READ
16
6C
ASI_L2_DIAG_TAG_READ_REG
16
6D
(JPS1)
16
6E
ASI_ERROR_IDENT (ASI_EIDR)
16
6F
ASI_C_LBSYR0
16
6F
ASI_C_LBSYR1
16
6F
ASI_C_BSTW0
16
6F
ASI_C_BSTW1
16
118 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
Type VA Description
RW 00
RW 08
R —
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R 08
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RW 00
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RW 10
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RW 28
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RW 38
W —
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R
00 -7FFC0
16 16
R TBD
RW —
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RW 08
RW 80
RW 88
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