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R
F. A P P E N D I X
UPA Programmer 's Model
This chapter describes the programmers model of the UPA interface of the
SPARC64 V. The registers for the UPA interface and the access method for those
registers are described. The appendix contains the following sections:
Mapping of the CPU's UPA Port Slave Area on page 213
UPA PortID Register on page 214
UPA Config Register on page 215
R.1
Mapping of the CPU's UPA Port Slave
Area
TABLE R-1
TABLE R-1
Relative Address
(Hex)
0 0000 0000
0 0000 0008
~ 1 FFFF FFFF
shows the mapping of the CPU's UPA port slave area.
CPU's UPA Port Slave Area Mapping
Length
Possible Access
8
Slave read from other
UPA port
--
None
Contents
UPA PortID Register; defined in
Section R.2.
Nothing. Write is ignored and
undefined value is read.
213
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