Cache Coherency Protocols; Cache Control/Status Instructions - Fujitsu SPARC JPS1 Implementation Supplement Manual

M.2

Cache Coherency Protocols

The CPU uses the UPA MOESI cache-coherence protocol; these letters are acronyms
for cache line states as follows:
M
O
E
S
I
A subset of the MOESI protocol is used in the on-chip caches as well as the D-Tags in
the system controller.
Relationships Between Cache Coherency Protocols
TABLE M-4
L2-Cache
Invalid (I)
Shared Clean (S)
Shared Modified (O)
Exclusive Clean (E)
Exclusive Modified (M)
TABLE M-5
TABLE M-5
Bit 2 (Valid)
0
1
1
1
1
M.3

Cache Control/Status Instructions

Several ASI instructions are defined to manipulate the caches. The following
conventions are common to all of the load and store alternate instructions defined in
this section:
128 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
Exclusive modified
Shared modified (owned)
Exclusive clean
Shared clean
Invalid
TABLE M-4
L1D-Cache
Invalid (I)
Invalid (I) or Clean (C)
Invalid (I)
Exclusive Modified (M)
shows the encoding of the MOESI states in the L2 Cache.
L2 Cache MOESI States
Bit 1 (Exclusive)
—
0
1
0
1
shows the relationships between the protocols.
SAT (store ownership)
Invalid (I)
Invalid (I)
Valid (V)
Bit 0 (Modified) State
— Invalid (I)
0 Shared clean (S)
0 Exclusive clean (E)
1 Shared modified (O)
1 Exclusive modified (M)
L1I-Cache
Invalid (I)
Invalid (I) or
Valid (V)