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7.3
Trap Control
Please refer to Section 7.3 of Commonality.
7.3.1
PIL Control
SPARC64 V receives external interrupts from the UPA interconnect. They cause an
interrupt_vector_trap
information and then schedules SPARC V9-compatible interrupts by writing bits in
the SOFTINT register. Please refer to Section 5.2.11 of Commonality for details.
During handling of SPARC V9-compatible interrupts by SPARC64 V, the PIL
register is checked. If an interrupt has sufficient priority, SPARC64 V will stop
issuing new instructions, will flush all uncommitted instructions, and then will
vector to the trap handler. The only exception to this process occurs when
SPARC64 V is processing a higher-priority trap.
SPARC64 V takes a normal disrupting trap upon receipt of an interrupt request.
7.4
Trap-Table Entry Addresses
Please refer to Section 7.4 of Commonality.
7.4.2
Trap Type (TT)
Please refer to Section 7.4.2 of Commonality.
SPARC64 V implements all mandatory SPARC V9 and SPARC JPS1 exceptions, as
described in Chapter 7 of Commonality, plus the exception listed in
is specific to SPARC64 V (impl. dep. #35; impl. dep. #36).
TABLE 7-1
Exception or Interrupt Request
async_data_error
38
SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
(TT = 60
). The interrupt vector trap handler reads the interrupt
16
Exceptions Specific to
SPARC64 V
TT
040
16
, which
TABLE 7-1
Priority
2
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