Fujitsu SPARC JPS1 Implementation Supplement Manual page 89

TABLE C-1
Nbr
227
228
229
230
231
232
233
234
235
236
237
238
239
78 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
SPARC64 V Implementation Dependencies (9 of 11)
SPARC64 V Implementation Notes
TSB number of entries
SPARC64 V
supports a maximum of 16 million entries in the common TSB
and a maximum of 32 million lines the Split TSB.
TSB_Hash supplied from TSB or context-ID register
TSB_Hash is generated from the context-ID register in
TSB_Base address generation
SPARC64 V
generates the TSB_Base address directly from the TLB
Extension Registers. By maintaining compatibility with UltraSPARC I/II,
SPARC64 V provides mode flag MCNTL.JPS1_TSBP. When
MCNTL.JPS1_TSBP = 0, the TSB_Base register is used.
data_access_exception
SPARC64 generates
data_access_exception
Section 7.6.1 of Commonality.
MMU physical address variability
SPARC64 V
supports both 41-bit and 43-bit physical address mode. The
initial width of the physical address is controlled by OPSR.
DCU Control Register CP and CV bits
SPARC64 V
does not implement CP and CV bits in the DCU Control
Register. See also impl. dep. #226.
TSB_Hash field
SPARC64 V
does not implement TSB_Hash.
TLB replacement algorithm
For fTLB, SPARC64 V implements a pseudo-LRU. For sTLB, LRU is used.
TLB data access address assignment
The MMU TLB data-access address assignment and the purpose of the
address are implementation dependent.
TSB_Size field width
SPARC64 V
In , TSB_Size is 4 bits wide, occupying bits 3:0 of the TSB
register. The maximum number of TSB entries is, therefore, 512
entries).
DSFAR/DSFSR for JMPL/RETURN
A
mem_address_not_aligned
instruction does not update either the D-SFAR or D-SFSR register.
TLB page offset for large page sizes
SPARC64 V
On , even for a large page, written data for TLB Data Register is
preserved for bits representing an offset in a page, so the data previously
written is returned regardless of the page size.
Register access by ASIs 55
SPARC64 V
In , VA<63:19> of IMMU ASI 55
ignored. An access to virtual addresses 40000
access 00000 to 20FF8
16 16
trap
only for the causes listed in
mem_address_not_aligned
exception that occurs during a JMPL or RETURN
and 5D
16 16
and DMMU ASI 5D
16
to 60FF8
16
Page
SPARC64 V
.
23, 91
15
2 (16M
89, 97
are
16
is treated as an
16
88
88
88
89
91
92
93
94
97
87
92