Asi_Eidr; Control Of Error Action (Asi_Error_Control) - Fujitsu SPARC JPS1 Implementation Supplement Manual

P.2.5

ASI_EIDR

The ASI_EIDR register designates the source ID in the ERROR_MARK_ID of the CPU.
[1]
[2]
[3]
[4]
[5]
ASI_EIDR
TABLE P-8
Bit Name
63:14 Reserved
13:0
ERROR_MARK_ID
P.2.6

Control of Error Action (ASI_ERROR_CONTROL)

Error detection masking and the action after error detection are controlled by the
value in ASI_ERROR_CONTROL, as defined in TABLE P-9.
[1]
[2]
[3]
[4]
[5]
[6]
The ASI_ERROR_CONTROL register controls error detection masking, error trap
occurrence masking, and the multiple-
described in
ASI_ERROR_CONTROL
TABLE P-9
Bit Name
9
RTE_UE
8
RTE_CEDG
Release 1.0, 1 July 2002
Register name:
ASI:
VA:
Error checking:
Format & function:
Bit Description
RW Description
R
RW
Register name:
ASI:
VA:
Error checking:
Format & function:
Initial value at reset:
.
TABLE P-9
Bit Description
RW Description
RW Restrainable Error Trap Enable submask for UE and Raw UE. The bit works as
defined in TABLE P-2
RW Restrainable Error Trap Enable submask for Corrected Error (
Degradation (
DG
ASI_EIDR
6E
16
00
16
Parity.
See .
TABLE P-8
Always 0.
ERROR_MARK_ID for the error caused by the CPU.
ASI_ERROR_CONTROL
4C
16
10
16
None
See .
TABLE P-9
Hard POR: ASI_ERROR_CONTROL.WEAK_ED is set to 1.
Other fields are set to 0.
Other resets: After UGE_HANDLER and WEAK_ED are copied
into ASI_STCHG_ERROR_INFO, all fields in
ASI_ERROR_CONTROL are set to 0.
trap occurrence. The register fields are
ADE
.
). The bit works as defined in
( ASI_ECR )
) and
CE
.
TABLE P-2
F. Chapter P Error Handling 161