Fujitsu SPARC JPS1 Implementation Supplement Manual page 173

ASI_ERROR_CONTROL
TABLE P-9
Bit Name
1
WEAK_ED
0
UGE_HANDLER
Other Reserved
162 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
Bit Description (Continued)
RW Description
RW Weak Error Detection. Controls whether the detection of
suppressed:
When WEAK_ED = 0, error detection is not suppressed.
When WEAK_ED = 1, error detection is suppressed if the CPU can continue
processing.
When or
I_UGE DAE
WEAK_ED = 1, the value of the output register or the store target memory
location become unpredictable.
Even if WEAK_ED = 1,
caused when the CPU cannot continue processing by ignoring the error.
WEAK_ED is the trap disabling mask for
defined in
TABLE P-2
When a multiple-
ASI_ERROR_CONTROL.UGE_HANDLER = 1), WEAK_ED is set to 1 by hardware.
RW Designates whether hardware can expect a
software (operating system) when a
0: Hardware recognizes that the privileged software
run.
1: Hardware expects that the privileged software
UGE_HANDLER is the trap disabling mask for
as defined in TABLE P-2
The value of UGE_HANDLER determines whether a multiple-
caused or not upon detection of
When an
async_data_error
When a RETRY or DONE instruction is completed, UGE_HANDLER is set to 0.
R Always reads as 0.
is detected during instruction execution while
or is detected and corresponding trap is
I_UGE DAE
A_UGE
.
trap is caused (
ADE I_UGE
UGE
.
,
I_UGE IAE
trap occurs, UGE_HANDLER is set to 1.
and
I_UGE
and restrainable errors, as
, , or detection while
IAE DAE
handler to run in privileged
UGE
error occurs:
handler does not
UGE
handler runs.
UGE
and restrainable errors,
A_UGE
trap is
ADE
, and .
DAE
is
DAE