Table of Contents
Advertisement
The MMU TLB data access address assignment and the purpose of the address on
SPARC64 V are shown in
TABLE F-4
VA Bit
17:16
15
13:3
Other
Release 1.0, 1 July 2002
TABLE F-4
MMU TLB Data Access Address Assignment
Field
Description
TLB to be accessed: fTLB or sTLB is designated as follows.
TLB#
00: fTLB (32 entries)
01: reserved
10: sTLB(2048 entries of 8-Kbyte page and 4-Mbyte page)
11: reserved
Error insertion into mTLB: When set on a write, an entry with
ER
parity error is inserted into a selected TLB location.
This field is ignored for a TLB entry read operation.
TLB index
Index number of the TLB. Specifies an index number for the TLB
reference. When fTLB is specified in TLB# field, the upper 6-bits of
the specified index are ignored.
When sTLB is specified in TLB# field, and
MCNTL.RMD = 00:
Index 0-511 addresses way0 of 8K-byte page sTLB
Index 512-1023 addresses way1 of 8K-byte page sTLB
MCNTL.RMD = 01:
Reserved. On all index, 0 is returned on read and writes
data is ignored.
MCNTL.RMD = 10:
Index 0-511 addresses way0 of 8K-byte page sTLB
Index 512-1023 addresses way1 of 8K-byte page sTLB
Index 1024-1535 addresses way0 of 4M-byte page sTLB
Index 1536-2047 addresses way1 of 4M-byte page sTLB
MCNTL.RMD = 11:
Index 0-511 addresses way0 of 8K-byte page sTLB
Index 512-1023 addresses way1 of 8K-byte page sTLB
Index 1024-1279 addresses way0 of 4M-byte page sTLB
Index 1536-1791 addresses way1 of 4M-byte page sTLB
Index 1280-1535 and 1792-2047 are reserved, 0 is returned
on read and writes data to this index is ignored.
FIGURE F-2 deipcts the relation of index number of sTLB and the
data to be accessed in various MCNTL.RMD.
When the entry to be written has a lock bit set and the specified
TLB is the sTLB, the entry is written into the sTLB with its lock bit
cleared. When the entry to be written into the fTLB, the entry is
written without lock bit modification.
Reserved
Ignored.
.
F. Chapter F
Memory Management Unit
95
Advertisement
Table of Contents
