Fatal Error And Error_State Transition Error; Asi_Stchg_Error_Info - Fujitsu SPARC JPS1 Implementation Supplement Manual

P.3 Fatal Error and error_state
Transition Error
P.3.1

ASI_STCHG_ERROR_INFO

The ASI_STCHG_ERROR_INFO register stores detected FATAL error and
error_state transition error information, for access by OBP (Open Boot PROM)
software.
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TABLE P-10
Format of
TABLE P-10
Bit Name
63:34 Reserved
33
ECR_WEAK_ED
32
ECR_UGE_HANDLER
31:15 Reserved
14 Always 0 (EE_OTHER)
13
EE_TRAP_ADDR_UNCORRECTED_ERROR
12
EE_OPSR
11
EE_WATCH_DOG_TIMEOUT_IN_MAXTL
10
EE_SECOND_WATCH_DOG_TIMEOUT
Release 1.0, 1 July 2002
Register name:
ASI:
VA:
Error checking:
Format & function:
Initial value at reset:
Update policy:
describes the fields in the ASI_STCHG_ERROR_INFO register.
ASI_STCHG_ERROR_INFO
ASI_STCHG_ERROR_INFO
4C
16
18
16
None
See
TABLE P-10
Hard POR: All fields are set to 0.
Other resets: Values are unchanged.
Upon detection of each related error, the corresponding bit in
ASI_STCHG_ERROR_INFO is set to 1. Writing 1 to bit 0 erases all
error indications in ASI_STCHG_ERROR_INFO (sets all bits in
the register, including bit 0, to 0).
Bit Description
RW Description
R Always 0.
R ASI_ERROR_CONTROL.WEAK_ED is copied into this
field at the beginning of a POR or watchdog reset.
R ASI_ERROR_CONTROL.UGE_HANDLER is copied into
this field at the beginning of the POR or watchdog
reset.
R Always 0.
R In the ideal case, EE_OTHER would be assigned in this
bit, but the field is not implemented in SPARC64 V.
R Upon detection of the corresponding error, set to 1.
R Upon detection of the corresponding error, set to 1.
R Upon detection of the corresponding error, set to 1.
R Upon detection of the corresponding error, set to 1.
F. Chapter P Error Handling 163