Fujitsu SPARC JPS1 Implementation Supplement Manual page 231

SPARC64 V and UltraSPARC-III Differences
TABLE T-1
Feature SPARC64 V
Floating-point In general, SPARC64 V does not
subnormal handle most subnormal operands
handling and results in hardware. However,
its handling differs from that of
UltraSPARC-III.
Block LD/ST SPARC64 V maintains register
implementation dependency between block load/
store and other instructions, but
hardware memory order constraint
is less than TSO.
Prefetch-invalidate is not
PREFETCH(A)
implementation implemented—SPARC64 V does
not implement a P-cache.
Prefetch with fcn = 20-23 causes a
trap on mDTLB miss.
Data cache Because SPARC64 V supports
flushing unaliasing by hardware, a flush of
data cache is not needed.
TPC/TNPC state Both TPC and TNPC values are
after power-on undefined after a power-on reset.
reset
W-cache SPARC64 V does not support a W-
cache.
P-cache SPARC64 V does not support a
P-cache.
UPA SPARC64 V uses ASI 4A
Configuration UPA configuration register.
ASI
SRAM test init Not supported.
D-cache Not supported.
E-cache ASIs 6B
cache diagnostic access.
Many differences.
ASI_AFSR
220 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
as the
16
and 6C support E-
16 16
(2 of 3)
SPARC64 V
Page UltraSPARC-III
65 In general, UltraSPARC-III does
not handle most subnormal
operands and results in
hardware. However, its handling
differs from that of SPARC64 V.
47 UltraSPARC-III does not
necessarily preserve memory or
register dependency ordering in
block load/store operations.
57 Implements prefetch-invalidate
(fcn = 16).
fcn = 20-23 does not cause a
trap. Equivalent to fcn = 0-3.
— Because the data cache uses one
virtual address bit for indexing, a
displacement flushing algorithm
or a cache diagnostic write is
required when a virtual address
alias is created.
141 TPC<5:0> is zero after any reset
trap. TNPC will be equal to
TNPC+4.
117 ASIs 38 –3B
16
diagnostic access to the W-cache.
117 ASIs 30 –33
16
access to the P-cache.
215 UltraSPARC-III does not support
UPA. Fireplane configuration
register is assigned in ASI 4A
— ASI 40 : not defined in manual. —
16
— ASIs 42 through 47
16
data cache diagnostic access.
130 ASIs 4B , 4E
16
and 7E support control over the
16
E-cache.
174 Many differences.
UltraSPARC-
III Section
B.6.1
A.4
A.49.1
1.4.4, M.2
C.2.5
provide L.3.2
16
provide diagnostic L.3.2
16
R.2
.
16
support L.3.2
16
, 74 , 75 , 76 , L.3.2
16 16 16 16
P.4.2