Table of Contents
Advertisement
ASI 4F
SPARC64 V provides eight of 64-bit registers that can be used temporary storage for
supervisor software.
[1]
[2]
[3]
[4]
Block Load and Store ASIs
ASIs E0
Commit operations (see Block Load and Store Instructions (VIS I) on page 47). Neither
ASI E0
LDDFA behaves as follows:
1. No exception is generated based on the destination register rd (impl. dep. #255).
2. For LDDFA with ASI E0
boundary, a SPARC64 V processor behaves as follows (impl. dep. #256):
n
generated, but a
n = 2 (4-byte alignment):
n 1 ( 2-byte alignment):
3. If the memory address is correctly aligned, a
AFSR.FTYPE = "invalid ASI" is generated.
Partial Store ASIs
ASIs C0
Store operations (see Partial Store (VIS I) on page 57). None of these ASIs should be
used with LDDFA; however, if one of them is used, the LDDFA behaves as follows on
a SPARC64 V processor (impl. dep. #257):
1. For LDDFA with C0
byte boundary, a SPARC64 V processor behaves as follows:
n
generated.
120
SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
(
ASI_SCRATCH_REGx
16
Register Name:
ASI:
VA:
RW:
and E1
exist only for use with STDFA instructions as Block Store with
16
16
nor ASI E1
should be used with LDDFA; however, if either is used, the
16
16
16
3 ( 8-byte alignment): no exception related to memory address alignment is
data_access_exception
–C5
and C8
–CD
16
16
16
–C5
16
16
3 ( 8-byte alignment): no exception related to memory address alignment is
)
Data<63:0>
ASI_SCRATCH_REGx (x = 0–7)
4F
16
VA<5:3> = register number
The other VA bits must be zero.
Supervisor read/write
or E1
and a memory address aligned on a 2
1
is generated (see case 3, below).
LDDF_mem_address_not_aligned
mem_address_not_aligned
data_access_exception
exist for use with the STDFA instruction for Partial
16
or C8
–CD
and a memory address aligned on a 2
16
16
n
-byte
exception is generated.
exception is generated.
with an
n
-
Advertisement
Table of Contents
