Fujitsu SPARC JPS1 Implementation Supplement Manual page 153

Nonprivileged and Privileged Register State after Reset and in
TABLE O-1
Name
TLE
CLE
<63:15>
TBA
PIL
CWP
FPRS
TL
TPC[TL]
TNPC[TL]
TSTATE CCR
ASI
PSTATE
CWP
PC
nPC
CANSAVE
CANRESTORE
OTHERWIN
CLEARWIN
WSTATE OTHER
NORMAL
VER MANUF
IMPL
MASK
MAXTL
MAXWIN
1.Hard POR occurs when power is cycled. Values are unknown following hard POR. Soft POR occurs when
UPA_RESET_L is asserted. Values are unchanged following soft POR.
2.The first watchdog timeout trap is taken in execute_state (i.e. PSTATE.RED = 0), subsequent watchdog timeout traps
as well as watchdog traps due to a trap @ TL = MAX_TL are taken in RED_state. See Section O.1.2, Watchdog Reset
(WDR), on page 138 for more details.
142 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
1
POR
0/ Copied from
CLE
0/ Unchanged
Unknown/Unchanged
Unknown/Unchanged
Unknown/Unchanged
Unknown/Unchanged
MAXTL
Unknown/Unchanged
Unknown/Unchanged
Unknown/Unchanged
Unknown/Unchanged
Unknown/Unchanged
Unknown/Unchanged
Unknown/Unchanged
Unknown/Unchanged
Unknown/Unchanged
0004
16
5
16
Mask dependent
5
16
7
16
2
WDR XIR
Copied from
CLE
Unchanged
Unchanged
Unchanged
Unchanged Unchanged
except for
register win-
dow traps
Unchanged
min
( + 1, )
TL MAXTL
PC
nPC
CCR
ASI
PSTATE
CWP
PC
nPC
Unchanged
Unchanged
Unchanged
Unchanged
Unchanged
Unchanged
(Continued)
RED_state
RED_state
SIR
Unchanged Unchanged
except for
register win-
dow traps