Fujitsu SPARC JPS1 Implementation Supplement Manual page 83

TABLE C-1
Nbr
32
33
34
35
36
37
38
39
40
41
72 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
SPARC64 V Implementation Dependencies (3 of 11)
SPARC64 V Implementation Notes
Deferred traps
SPARC64 V signals a deferred trap in a few of its severe error conditions.
SPARC64 V does not contain a deferred trap queue.
Trap precision
There are no deferred traps in
few severe error conditions. All traps that occur as the result of program
execution are precise.
Interrupt clearing
For details of interrupt handling see Appendix N, Interrupt Handling.
Implementation-dependent traps
SPARC64 V
supports the following traps that are implementation
dependent:
• (tt = 060
interrupt_vector_trap
• (tt = 061
PA_watchpoint
• (tt = 062
VA_watchpoint
• (tt = 063
ECC_error
16
•
fast_instruction_access_MMU_miss
•
fast_data_access_MMU_miss
•
fast_data_access_protection
• (tt = 040
async_data_error
Trap priorities
SPARC64 V
's implementation-dependent traps have the following
priorities:
• (priority = 16)
interrupt_vector_trap
• (priority = 12)
PA_watchpoint
• (priority = 1)
VA_watchpoint
• (priority = 33)
ECC_error
•
fast_instruction_access_MMU_miss
• fast_data_access_MMU_miss
•
fast_data_access_protection
• (priority = 2)
async_data_error
Reset trap
SPARC64 V implements power-on reset (POR) and watchdog reset.
Effect of reset trap on implementation-dependent registers
See Section O.3, Processor State after Reset and in RED_state, on page 141.
Entering error_state on implementation-dependent errors
CPU watchdog timeout at 2
causes the CPU to enter error_state.
Error_state processor state
SPARC64 V
optionally takes a watchdog reset trap after entry to
error_state. Most error-logging register state will be preserved. (See also
impl. dep. #254.)
Reserved.
SPARC64 V
other than the trap caused by a
)
16
)
16
)
16
)
(tt = 064
16
(tt = 068 through 06B
16
(tt = 06C through 06F
16
)
16
(priority = 2)
(priority = 12)
(priority = 12)
33
ticks, a normal trap, or an SIR at TL = MAXTL
through 067 )
16
)
16
)
16
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