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F
F. A P P E N D I X
Memory Management Unit
The Memory Management Unit (MMU) architecture of SPARC64 V conforms to the
MMU architecture defined in Appendix F of Commonality but with some model
dependency. See Appendix F in Commonality for the basic definitions of the
SPARC64 V MMU.
Section numbers in this appendix correspond to those in Appendix F of
Commonality. Figures and tables, however, are numbered consecutively.
This appendix describes the implementation dependencies and other additional
information about the SPARC64 V MMU. For SPARC64 V implementations, we first
list the implementation dependency as given in
describe the SPARC64 V implementation.
F.1
Virtual Address Translation
IMPL. DEP. #222
SPARC64 V has the following TLB organization:
TABLE F-1
Hardware contains micro-ITLB and micro-DTLB as the temporary memory of the
main TLBs, as shown in
are called main TLBs.
: TLB organization is JPS1 implementation dependent.
Level-1 micro ITLB (uITLB), 32-way fully associative
Level-1 micro DTLB (uDTLB), 32-way fully associative
Level-2 IMMU-TLB consists of sITLB (set-associative Instruction TLB) and
fITLB (fully associative Instruction TLB).
Level-2 DMMU-TLB consists of sDTLB (set-associative Data TLB) and fDTLB
(fully associative Data TLB).
shows the organization of SPARC64 V TLBs.
TABLE C-1
. In contrast to the micro-TLBs, sTLB and fTLB
TABLE F-1
of Commonality, then
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