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Fujitsu SPARC JPS1 Implementation Supplement Manual

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Fujitsu Limited
4-1-1 Kamikodanaka
Nahahara-ku, Kawasaki, 211-8588
Japan
Part No. 806-6755-1.0
SPARC JPS1
Implementation Supplement:
Fujitsu SPARC64 V
Fujitsu Limited
Release 1.0, 1 July 2002

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  • Page 1 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V Fujitsu Limited Release 1.0, 1 July 2002 Fujitsu Limited 4-1-1 Kamikodanaka Nahahara-ku, Kawasaki, 211-8588 Japan Part No. 806-6755-1.0...
  • Page 2 This product and related documentation are protected by copyright and distributed under licenses restricting their use, copying, distribution, and decompilation. No part of this product or related documentation may be reproduced in any form by any means without prior written authorization of Fujitsu Limited and its licensors, if any.
  • Page 3 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 4: Table Of Contents

    F. C H A P T E R Contents Overview 1 Navigating the SPARC64 V Implementation Supplement 1 Fonts and Notational Conventions 1 The SPARC64 V processor 2 Component Overview 4 Instruction Control Unit (IU) 6 Execution Unit (EU) 6 Storage Unit (SU) 7 Secondary Cache and External Access Unit (SXU) 8 Definitions 9...
  • Page 5 Trap Type (TT) 38 Details of Supported Traps 39 Trap Processing 39 Exception and Interrupt Descriptions 39 SPARC V9 Implementation-Dependent, Optional Traps That Are Mandatory in SPARC JPS1 39 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 6 SPARC JPS1 Implementation-Dependent Traps 39 Memory Models 41 Overview 42 SPARC V9 Memory Model 42 Mode Control 42 Synchronizing Instruction and Data Memory 42 A. Instruction Definitions: SPARC64 V Extensions 45 Block Load and Store Instructions (VIS I) 47 Call and Link 49 Implementation-Dependent Instructions 49 Floating-Point Multiply-Add/Subtract 50 Jump and Link 53...
  • Page 7 Special Memory Access ASIs 119 Barrier Assist for Parallel Processing 121 Interface Definition 121 ASI Registers 122 M. Cache Organization 125 Cache Types 125 Level-1 Instruction Cache (L1I Cache) 126 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 8 Level-1 Data Cache (L1D Cache) 127 Level-2 Unified Cache (L2 Cache) 127 Cache Coherency Protocols 128 Cache Control/Status Instructions 128 Flush Level-1 Instruction Cache (ASI_FLUSH_L1I) 129 Level-2 Cache Control Register (ASI_L2_CTRL) 130 L2 Diagnostics Tag Read (ASI_L2_DIAG_TAG_READ) 130 L2 Diagnostics Tag Read Registers (ASI_L2_DIAG_TAG_READ_REG) 131 N.
  • Page 9 Handling of a D1 Cache Data Error 190 Handling of a U2 Cache Data Error 192 Automatic Way Reduction of I1 Cache, D1 Cache, and U2 Cache 193 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 10 TLB Error Handling 195 Handling of TLB Entry Errors 195 Automatic Way Reduction of sTLB 196 Handling of Extended UPA Bus Interface Error 197 Handling of Extended UPA Address Bus Error 197 Handling of Extended UPA Data Bus Error 197 Q.
  • Page 11 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 12: Overview

    F. C H A P T E R Overview Navigating the SPARC64 V Implementation Supplement We suggest that you approach this Implementation Supplement SPARC Joint Programming Specification as follows. 1. Familiarize yourself with the SPARC64 V processor and its components by reading these sections: The SPARC64 V processor on page 2 Component Overview on page 4...
  • Page 13: The Sparc64 V Processor

    It contributes to higher reliability by eliminating the external connections for level-2 cache. High Reliability and High Integrity SPARC64 V implements the following advanced RAS features for reliability and integrity beyond that of ordinary microprocessors. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 14 1. Advanced RAS features for caches Strong cache error protection: ECC protection for D1 (Data level 1) cache data, U2 (unified level 2) cache data, and the U2 cache tag. Parity protection for I1 (Instruction level 1) cache data. Parity protection and duplication for the I1 cache tag and the D1 cache tag. Automatic correction of all types of single-bit error: Automatic single-bit error correction for the ECC protected data.
  • Page 15: Component Overview

    Instruction control Unit (IU) Execution Unit (EU) Storage Unit (SU) Secondary cache and eXternal access Unit (SXU) illustrates the major units; the following subsections describe them. FIGURE 1-1 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 16 Extended UPA Bus SX-Unit E-Unit UPA interface logic MoveOut buffer MoveIn buffer U2$ data ALUs 2M 4-way Input Registers S-Unit interface Output Registers S-Unit EAGA EAGB SX interface SX order queue Store queue I-TLB data D-TLB data 2048 2048 Level-1 I cache Level-1 D cache + 32 + 32...
  • Page 17: Instruction Control Unit (Iu)

    Fr architecture register file (FPR) Thirty-two entries, 6 read ports, 2 write ports EU control logic Controls the instruction execution stages: instruction selection, register read, and execution. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 18: Storage Unit (Su)

    Execution Unit Major Blocks (Continued) TABLE 1-2 Name Description Interface registers Input/output registers to other units. Two integer execution pipelines 64-bit ALU and shifters. (EXA, EXB) Two floating-point and graphics Each floating-point execution pipeline can execute floating execution pipelines (FLA, FLB) point multiply, floating point add/sub, floating-point multiply and add, floating point div/sqrt, and floating- point graphics instruction.
  • Page 19: Secondary Cache And External Access Unit (Sxu)

    Eight entries, 64-bytes/entry; holds writeback data. A maximum of 8 outstanding writeback requests can be issued. Extended UPA interface Send/receive transaction packets to/from Extended UPA control logic interface connected to the system. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 20: Definitions

    F. C H A P T E R Definitions This chapter defines concepts unique to the SPARC64 V, the Fujitsu implementation of SPARC JPS1. For definition of terms that are common to all implementations, please refer to Chapter 2 of Commonality.
  • Page 21 Before instructions are issued, source and destination registers are mapped onto this set of rename registers. This allows instructions that normally would be blocked, waiting for an architected register, to proceed SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 22 in parallel. When instructions are committed, results in renamed registers are posted to the architected registers in the proper sequence to produce the correct program results. scan A method used to initialize all of the machine state within a chip. In a chip that has been designed to be scannable, all of the machine state is connected in one or several loops called “scan rings.”...
  • Page 23 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 24: Architectural Overview

    F. C H A P T E R Architectural Overview Please refer to Chapter 3 in the Commonality section of SPARC Joint Programming Specification.
  • Page 25 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 26: Data Formats

    F. C H A P T E R Data Formats Please refer to Chapter 4, Data Formats in Commonality.
  • Page 27 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 28: Registers

    F. C H A P T E R Registers The SPARC64 V processor includes two types of registers: general-purpose—that is, working, data, control/status—and ASI registers. The SPARC V9 architecture also defines two implementation-dependent registers: the IU Deferred-Trap Queue and the Floating-Point Deferred-Trap Queue (FQ); SPARC64 V does not need or contain either queue.
  • Page 29: Floating-Point State Register (Fsr)

    In SPARC64 V, the cexc bits are set according to the following pseudocode: if (<LDFSR or LDXFSR commits>) <update using data from LDFSR or LDXFSR>; else if (<FPop commits with ftt = 0>) <update using value from FPU> SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 30: Tick (Tick) Register

    else if (<FPop commits with IEEE_754_exception>) <set one bit in the CEXC field as supplied by FPU>; else if (<FPop commits with unfinished_FPop error>) <no change>; else if (<FPop commits with unimplemented_FPop error>) <no change>; else <no change>; FSR Conformance SPARC V9 allows the TEM, cexc, and aexc fields to be implemented in hardware in either of two ways (both of which comply with IEEE Std 754-1985).
  • Page 31: Version (Ver) Register

    The manuf field contains Fujitsu’s 8-bit JEDEC code in the lower 8 bits and zeroes in the upper 8 bits. The manuf, impl, and mask fields are implemented so that they may change in future SPARC64 V processor versions. The mask field is incremented by 1 any time a programmer-visible revision is made to the processor.
  • Page 32 The Performance Control Register in SPARC64 V is illustrated in FIGURE 5-1 described in TABLE 5-2 OVRO ULRO UT ST PRIV 10 9 SPARC64 V Performance Control Register (PCR) (ASR 16) FIGURE 5-1 Bit Description TABLE 5-2 Field Description 47:32 Overflow Clear/Set/Status.
  • Page 33: Registers Referenced Through Asis

    The functions include Instruction, Prefetch, write and data caches, MMUs, and watchpoint setting. SPARC64 V implements most of DCUCUR’s functions described in Section 5.2.12 of Commonality. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 34 After a power-on reset (POR), all fields of DCUCR, including implementation- dependent fields, are set to 0. After a WDR, XIR, or SIR reset, all fields of DCUCR, including implementation-dependent fields, are set to 0. The Data Cache Unit Control Register is illustrated in and described in FIGURE 5-2 .
  • Page 35: Floating-Point Deferred-Trap Queue (Fq)

    An attempt to read FQ with an RDPR instruction generates an illegal_instruction exception (impl. dep. #25). 5.2.14 IU Deferred-Trap Queue SPARC64 V neither has nor needs an IU deferred-trap queue (impl. dep. #16) SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 36: Instructions

    F. C H A P T E R Instructions This chapter presents SPARC64 V implementation-specific instruction details and the processor pipeline information in these subsections: Instruction Execution on page 25 Instruction Formats and Fields on page 28 Instruction Categories on page 29 Processor Pipeline on page 31 For additional, general information, please see parallel subsections of Chapter 6 in Commonality.
  • Page 37: Instruction Prefetch

    (in program order) have been committed. 1. Hardware errors and other asynchronous errors may generate a trap even if the instruction that caused the trap is never committed. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 38: Syncing Instructions

    6.1.3 Syncing Instructions SPARC64 V has instructions, called syncing instructions, that stop execution for the number of cycles it takes to clear the pipeline and to synchronize the processor. There are two types of synchronization, pre and post. A presyncing instruction waits for all previous instructions to commit, commits by itself, and then issues successive instructions.
  • Page 39: Instruction Formats And Fields

    This 2-bit field specifies which specific operation (variation) to perform for the floating-point multiply-add and multiply-subtract instructions This 2-bit field specifies the size of the operands for the floating-point size multiply-add and multiply-subtract instructions. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 40: Instruction Categories

    Since = 00 is not IMPDEP2B and since size = 11 assumed quad operations but size is not implemented in SPARC64 V, the instruction with size = 00 or 11 generates an exception in SPARC64 V. illegal_instruction Instruction Categories SPARC V9 instructions comprise the categories listed below. All categories are described in Section 6.3 of Commonality.
  • Page 41: Floating-Point Operate (Fpop) Instructions

    SPARC V9 architecture, the operating system does not supply software emulation routines for the quad versions of these instructions. SPARC64 V uses the IMPDEP1 instruction to implement the graphics acceleration instructions. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 42: Processor Pipeline

    Processor Pipeline The pipeline of SPARC64 V consists of fifteen stages, shown in FIGURE 6-2. Each stage is referenced by one or two letters as follows: 6.4.1 Instruction Fetch Stages IA (Instruction Address generation) — Calculate fetch target address. IT (Instruction TLB Tag access) — Instruction TLB tag search. Search of BRHIS and RAS is also started.
  • Page 43 IF EAG iTLB BRHIS Instruction Buffer RSFA RSFB RSEA RSEB RSBR EAGA EAGB dTLB ccr fsr PC nPC SPARC64 V Pipeline FIGURE 6-2 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 44: Issue Stages

    6.4.2 Issue Stages E (Entry) — Instructions are passed from fetch stages. D (Decode) — Assign resources and dispatch to reservation station (RS.) SPARC64 V is an out-of-order execution CPU. It has six execution units (two of arithmetic and logic unit, two of floating-point unit, two of load/store unit). Each unit except the load/store unit has its own reservation station.
  • Page 45: Completion Stages

    Exception handling is done in the completion stages. Exceptions occurring in execution stages are not handled immediately but are signalled when the instruction is completed. 1. RAS-related exception may be signalled before completion. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 46: Traps

    F. C H A P T E R Traps Please refer to Chapter 7 of Commonality. Section numbers in this chapter correspond to those in Chapter 7 of Commonality. This chapter adds SPARC64 V-specific information in the following sections: Processor States, Normal and Special Traps on page 35 RED_state on page 36 error_state on page 36 Trap Categories on page 37...
  • Page 47: Red_State

    The processor enters error_state when a trap occurs while the processor is already at its maximum supported trap level (that is, when TL = MAXTL) (impl. dep. #39). SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 48: Trap Categories

    Although the standard behavior of the CPU upon an entry into error_state is to internally generate a (WDR), the CPU optionally stays halted upon an watchdog_reset entry to error_state depending on a setting in the OPSR register (impl. dep #40, #254).
  • Page 49: Trap Control

    , which TABLE 7-1 is specific to SPARC64 V (impl. dep. #35; impl. dep. #36). SPARC64 V Exceptions Specific to TABLE 7-1 Exception or Interrupt Request Priority async_data_error SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 50: Details Of Supported Traps

    7.4.4 Details of Supported Traps Please refer to Section 7.4.4 in Commonality. SPARC64 V Implementation-Specific Traps SPARC64 V supports the following implementation-specific trap type: async_data_error Trap Processing Please refer to Section 7.5 of Commonality. Exception and Interrupt Descriptions Please refer to Section 7.6 of Commonality. 7.6.4 SPARC V9 Implementation-Dependent, Optional Traps That Are Mandatory in SPARC JPS1...
  • Page 51 TNPC stacked by the exception may indicate the exact instruction, the preceding instruction, or the subsequent instruction inducing the error. See Appendix P for details of the exception in SPARC64 V. async_data_error SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 52: Memory Models

    F. C H A P T E R Memory Models The SPARC V9 architecture is a model that specifies the behavior observable by software on SPARC V9 systems. Therefore, access to memory can be implemented in any manner, as long as the behavior observed by software conforms to that of the models described in Chapter 8 of Commonality and defined in Appendix D, Formal Specification of the Memory Models, also in Commonality.
  • Page 53: Sparc V9 Memory Model

    All caches in a SPARC64 V-based system (uniprocessor or multiprocessor) have a unified cache consistency protocol and implement strong coherence between instruction and data caches. Writes to any data cache cause invalidations to the SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 54 corresponding locations in all instruction caches; references to any instruction cache cause corresponding modified data to be flushed and corresponding unmodified data to be invalidated from all data caches. The flush operation is still operative in SPARC64 V, however. Since the FLUSH instruction synchronizes the processor, the total latency varies depending on the situation in SPARC64 V.
  • Page 55 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 56 F. A P P E N D I X Instruction Definitions: SPARC64 V Extensions This appendix describes the SPARC64 V-specific implementation of the instructions in Appendix A of Commonality. If an instruction is not described in this appendix, then no SPARC64 V implementation-dependency applies. of Commonality for the location at which general information about TABLE A-1 the instruction can be found.
  • Page 57 Prefetch Data on page 57 Read State Register on page 58 SHUTDOWN (VIS I) on page 58 Write State Register on page 59 Deprecated Instructions on page 59 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 58: Block Load And Store Instructions (Vis I)

    Block Load and Store Instructions (VIS I) The following notes summarize behavior of block load/store instructions in SPARC64 V. 1. Block load and store operations are not atomic, in that they are internally decomposed into eight independent, 8-byte load/store operations in SPARC64 V. Each load/store is always issued and performed in the RMO memory model and obeys all prior MEMBAR and atomic instruction-imposed ordering constraints.
  • Page 59 (see Block Load and Store ASIs on page 120) mem_address_not_aligned (see Block Load and Store ASIs on page 120) data_access_exception (see Block Load and Store ASIs on page 120) LDDF_mem_address_not_aligned data_access_error fast_data_access_MMU_miss fast_data_access_protection SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 60: Call And Link

    A.12 Call and Link SPARC64 V clears the upper 32 bits of the PC value in r[15] when PSTATE.AM is set (impl. dep. #125). The value written into r[15] is visible to the instruction in the delay slot. SPARC64 V has a special hardware table, called the return address stack, to predict the return address from a subroutine.
  • Page 61: Floating-Point Multiply-Add/Subtract

    , freg fnmadds freg , freg , freg , freg fnmaddd freg , freg , freg , freg fnmsubs freg , freg , freg , freg fnmsubd SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 62 Description The Floating-point Multiply-Add instructions multiply the registers specified by the rs1 field times the registers specified by the rs2 field, add that product to the registers specified by the rs3 field, then write the result into the registers specified by the rd field.
  • Page 63 In the tables, the conditions in the shaded columns are all reported as an trap by SPARC64 V. In addition, the conditions with “ ” do not — unfinished_FPop exist. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 64: Jump And Link

    Programming Note – The Multiply Add/Subtract instructions are encoded in the SPARC V9 IMPDEP2 opcode space, and they are specific to the SPARC64 V implementation. They cannot be used in any programs that will be executed on any other SPARC V9 processor, unless that implementation exactly matches the SPARC64 V use for the IMPDEP2 opcode.
  • Page 65: Load Quadword, Atomic [Physical]

    Quadword Atomic for virtually addressed data (ASIs 24 and 2C The memory access for a load quad instruction with ASI_QUAD_LDD_PHYS{_L} behaves as if the following TTE is set: SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 66: Memory Barrier

    TTE.NFO = 0 TTE.CP = 1 TTE.CV = 0 TTE.E TTE.P TTE.W Note – TTE.IE depends on the endianness of the ASI. When the ASI is 034 TTE.IE = 0; TTE.IE = 1 when the ASI is 03C Therefore, the atomic quad load physical instruction can only be applied to a cacheable memory area.
  • Page 67 A store appearing before the MEMBAR must complete before cmask<0> barrier any load following the MEMBAR referencing the same address can be initiated. Equivalent to #Sync in SPARC64 V. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 68: Partial Store (Vis I)

    A.42 Partial Store (VIS I) Please refer A.42 in Commonality for general details. Watchpoint exceptions on partial store instructions occur conservatively on SPARC64 V. The DCUCR Data Watchpoint masks are only checked for nonzero value (watchpoint enabled). The byte store mask (r[rs2]) in the partial store instruction is ignored, and a watchpoint exception can occur even if the mask is zero (that is, no store will take place) (impl.
  • Page 69: Read State Register

    RDPCR will not cause any access privilege violation exception (impl. dep. #250). A.70 SHUTDOWN (VIS I) In SPARC64 V, SHUTDOWN acts as a NOP in privileged mode (impl. dep. #206). SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 70: Write State Register

    A.70 Write State Register In SPARC64 V, a WRPCR instruction will cause a exception if privileged_action PSTATE.PRIV = 0 and PCR.PRIV = 1. If PSTATE.PRIV = 0 and PCR.PRIV = 0, WRPCR causes a exception only when an attempt is made to change privileged_action (that is, write 1 to) PCR.PRIV (impl.
  • Page 71 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 72: Traps Inhibiting Results

    F. A P P E N D I X IEEE Std 754-1985 Requirements for SPARC V9 The IEEE Std 754-1985 floating-point standard contains a number of implementation dependencies. Please see Appendix B of Commonality for choices for these implementation dependencies, to ensure that SPARC V9 implementations are as consistent as possible.
  • Page 73 When the result is expected to be a constant, such as an exact zero or an infinity, and an insignificant computation will furnish the result, SPARC64 V tries to calculate the result without signalling an exception. unfinished_FPop SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 74 Implementation Note – Detecting the exact boundary conditions requires a large amount of hardware. SPARC64 V detects approximate boundary conditions by calculating the exponent intermediate result (the exponent before rounding) from input operands, to avoid the hardware cost. Since the computation of the boundary conditions is approximate, the detection of a zero result or an overflow result shall be pessimistic.
  • Page 75 SPARC64 V generates the result as a pessimistic TABLE B-3 zero, meaning that the result is a denormalized minimum or a zero, depending on the rounding mode (FSR.RD). SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 76: Operation Under Fsr.ns = 1

    Conditions for a Pessimistic Zero TABLE B-3 Conditions Operations One operand is denormalized Both are denormalized Both are normal fp-number always — eres FdTOs single precision: Er Always single precision: eres FMULs, FMULd double precision: Er double precision: eres single precision: Er Never single precision: eres FDIVs,...
  • Page 77 4. If the FPop is either FADD{s,d}, or FSUB{s,d} and the operation is 0 ± denormalized number, SPARC64 V does not generate an unfinished_FPop and generates a result according to IEEE754-1985 standard. 5. Nmax = normalized maximum. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 78 describes how SPARC64 V behaves when FSR.NS = 1 (nonstandard mode). TABLE B-6 Nonarithmetic Operations Under FSR.NS = 1 TABLE B-6 op2= Operations op1= denorm denorm Result — — — — FsTOd — — nx, a signed zero — — —...
  • Page 79 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 80: Definition Of An Implementation Dependency

    F. A P P E N D I X Implementation Dependencies This appendix summarizes implementation dependencies. In SPARC V9 and SPARC JPS1, the notation “IMPL. DEP. #nn:” identifies the definition of an implementation dependency; the notation “(impl. dep. #nn)” identifies a reference to an implementation dependency.
  • Page 81: Hardware Characteristics

    This dependency is beyond the scope of this publication. It should be SPARC64 V defined in each system that uses RDASR/WRASR target registers — See A.50 and A.70 in Commonality for details of implementation-dependent RDASR/WRASR instructions. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 82 SPARC64 V Implementation Dependencies (2 of 11) TABLE C-1 SPARC64 V Implementation Notes Page RDASR/WRASR privileged status — See A.50 and A.70 in Commonality for details of implementation-dependent RDASR/WRASR instructions. 10–12 Reserved. VER.impl SPARC64 V VER.impl = 5 for the processor.
  • Page 83 Error_state processor state SPARC64 V optionally takes a watchdog reset trap after entry to error_state. Most error-logging register state will be preserved. (See also impl. dep. #254.) Reserved. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 84 • Prefetches will work normally if the ASI is ASI_PRIMARY, ASI_SECONDARY, or ASI_NUCLEUS, ASI_PRIMARY_AS_IF_USER, ASI_SECONDARY_AS_IF_USER, and their little-endian pairs. VER.manuf VER.manuf = 0004 . The least significant 8 bits are Fujitsu’s JEDEC manufacturing code. TICK register SPARC64 V implements 63 bits of the TICK register; it increments on every clock cycle.
  • Page 85 Prefetch and nonfaulting Load always succeed when the MMU is disabled. Identifying I/O locations — This dependency is beyond the scope of this publication. It should be SPARC64 V defined in a system that uses SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 86 SPARC64 V Implementation Dependencies (6 of 11) TABLE C-1 SPARC64 V Implementation Notes Page Unimplemented values for PSTATE.MM Writing 11 into PSTATE.MM causes the machine to use the TSO memory model. However, the encoding 11 should not be used, since future versions SPARC64 V may use this encoding for a new memory model.
  • Page 87 — data_access_error SPARC64 V data_access_error trap is always precise in trap precision — instruction_access_error trap is always precise in SPARC64 V instruction_access_error SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 88 SPARC64 V Implementation Dependencies (8 of 11) TABLE C-1 SPARC64 V Implementation Notes Page async_data_error SPARC64 V trap is implemented in , using tt = 40 . See async_data_error Appendix P for details. Asynchronous Fault Address Register ( AFAR ) allocation 177, 178 SPARC64 V implements two AFARs:...
  • Page 89 , VA<63:19> of IMMU ASI 55 and DMMU ASI 5D ignored. An access to virtual addresses 40000 to 60FF8 is treated as an access 00000 to 20FF8 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 90 SPARC64 V Implementation Dependencies (10 of 11) TABLE C-1 SPARC64 V Implementation Notes Page DCU Control Register bits 47:41 SPARC64 V uses bit 41 for WEAK_SPCA, which enables/disables memory access in speculative paths. Address Masking and DSFAR — SPARC64 V writes zeroes to the more significant 32 bits of DSFAR.
  • Page 91 = 2 (4-byte alignment): exception is LDDF_mem_address_not_aligned generated. 1 ( 2-byte alignment): exception is mem_address_not_aligned generated. ASI_SERIAL_ID SPARC64 V provides an identification code for each processor. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 92 F. A P P E N D I X Formal Specification of the Memory Models Please refer to Appendix D of Commonality.
  • Page 93 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 94: E. Opcode Maps

    F. A P P E N D I X Opcode Maps Please refer to Appendix E in Commonality. lists the opcode map for the TABLE E-1 SPARC64 V IMPDEP2 instruction. IMPDEP2 (op = 2, op3 = 37 TABLE E-1 var (instruction <8:7>) (not used —...
  • Page 95 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 96: Virtual Address Translation

    F. A P P E N D I X Memory Management Unit The Memory Management Unit (MMU) architecture of SPARC64 V conforms to the MMU architecture defined in Appendix F of Commonality but with some model dependency. See Appendix F in Commonality for the basic definitions of the SPARC64 V MMU.
  • Page 97: Translation Table Entry (Tte)

    U2 cache and generates a UPA request for the cacheable access. The urgent error ASI_UGESR.SDC is signalled after the UPA cacheable access is requested. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 98 The physical address length to be passed to the UPA interface is 41 bits or 43 bits, as designated in the ASI_UPA_CONFIG.AM field. When the 41-bit PA is specified in ASI_UPA_CONFIG.AM, the most significant 2 bits of the CPU internal physical address are discarded and only the remaining least significant 41 bits are passed to the UPA address bus.
  • Page 99: Tsb Organization

    For a shared TSB (TSB Register split field = 0): 8K_POINTER = TSB_Extension[63:13+N] (VA[21+N:13] TSB_Hash) 0000 64K_POINTER = TSB_Extension[63:13+N] (VA[24+N:16] TSB_Hash) 0000 For a split TSB (TSB Register split field = 1): SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 100: Faults And Traps

    8K_POINTER = TSB_Extension[63:14+N] (VA[21+N:13] TSB_Hash) 0000 64K_POINTER = TSB_Extension[63:14+N] (VA[24+N:16] TSB_Hash) 0000 Value of TSB_Hash for both a shared TSB and a split TSB When 0 <= N <= 4, TSB_Hash = context_register[N+8:0] Otherwise, when 5 <= N <= 15, TSB_Hash[ 12:0 ] = context_register[ 12:0 ] TSB_Hash[ N+8:13 ] = 0 ( N-4 bits zero ) Faults and Traps...
  • Page 101 A bus error response from the UPA bus is detected upon an operand access. mDTLB (sDTLB and fDTLB) multiple hits are detected in an mDTLB lookup for an operand access. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 102: Reset, Disable, And Red_State Behavior

    An fDTLB entry parity error is detected in a fDTLB lookup for an instruction operand access. Reset, Disable, and RED_state Behavior : The variability of the width of physical address is implementation IMPL. DEP. #231 dependent in JPS1, and if variable, the initial width of the physical address after reset is also implementation dependent in JPS1.
  • Page 103: Internal Registers And Asi Operations

    FIGURE F-1 TABLE F-3 ASI_MCNTL (Memory Control Register) ASI: Access Modes: Supervisor read/write reserved JPS1_TSBP 00000000 Cache fITLB fDTLB 13 12 11 Format of ASI_MCNTL FIGURE F-1 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 104: I/D Tlb Data In, Data Access, And Tag Read Registers

    Field Description MCNTL TABLE F-3 Bits Field Name Description Force instruction caching. When set, the instruction lines fetched from a Data <16> NC_Cache noncacheable area are cached in the instruction cache. The NC_Cache has no effect on operand references. If MCNTL.NC_Cache = 1, the CPU fetches a noncacheable line in four consecutive 16-byte fetches and stores the entire 64 bytes in the I-Cache.
  • Page 105 For fTLB, SPARC64 V implements a pseudo-LRU. For sTLB, LRU is used. : The MMU TLB data access address assignment and the purpose of IMPL. DEP. #235 the address are implementation dependent in JPS1. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 106 The MMU TLB data access address assignment and the purpose of the address on SPARC64 V are shown in TABLE F-4 MMU TLB Data Access Address Assignment TABLE F-4 VA Bit Field Description 17:16 TLB to be accessed: fTLB or sTLB is designated as follows. TLB# 00: fTLB (32 entries) 01: reserved...
  • Page 107 Kbyte page, bits[21:13] is conscidered as index and compared with the index field of TLB Data Access or Data In Register. In 4-Mbyte page, bits[30:22] when MCNTL.RMD=10, or bits[29:22] when MCNTL.RMD=11, is conscidered as index. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 108: I/D Tsb Extension Registers

    I/D TSB Base Registers : The width of the TSB_Size field in the TSB Base Register is IMPL. DEP. #236 implementation dependent; the permitted range is from 2 to 6 bits. The least significant bit of TSB_Size is always at bit 0 of the TSB Base Register. Any bits unimplemented at the most significant end of TSB_Size read as 0, and writes to them are ignored.
  • Page 109 This field is valid for the exception in which the ISFSR.FV bit is set. A recorded ASI is 80 (ASI_PRIMARY) or 04 (ASI_NUCLEUS) depending on the trap level (when TL > 0, the ASI is ASI_NUCLEUS.). SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 110 Bit Description -SFSR TABLE F-5 Bits Field Name Description Data <15> Translation miss. When TM = 1, it signifies an occurrence of a mITLB miss upon an instruction reference. Data <13:7> Fault type. Saves and indicates an exact condition that caused the recorded FT<6:0>...
  • Page 111 TLB. The priority of error logging for multiple error conditions (parity error and multiple-hit error) is as follows: fTLB parity high sTLB parity sTLB-multihit fTLB-multihit The smaller index number is selected for multiple hits. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 112 D-SFSR Bit Description (2 of 3) TABLE F-8 Bits Field Name Description Data <46> Marked . On SPARC64 V, all uncorrectable errors are reported as marked, so this bit is always set whenever DSFSR.UE = 1. See Section P.2.4 for details. Data <45:32>...
  • Page 113 An attempt was made to access a noncacheable page or an internal ASI by an atomic instruction (CASA, CASXA, SWAP, SWAPA, LDSTUB, LDSTUBA) or an atomic quad load instruction (LDDA with ASI = 024 , 02C , 034 , or 03C SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 114 MMU Synchronous Fault Status Register FT (Fault Type) Field (Continued) TABLE F-9 FT<6:0> Error Description An attempt was made to access an alternate address space with an illegal ASI value, an illegal VA, an invalid read/write attribute, or an illegally sized operand.
  • Page 115: Mmu Bypass

    TABLE on SPARC64 V Bypass Attribute Bits TABLE F-11 Attribute Bits NAME VALUE CP Size 8 Kbytes ASI_PHYS_USE_EC ASI_PHYS_USE_EC_LITTLE ASI_PHYS_BYPASS_EC_WITH_EBIT 8 Kbytes ASI_PHYS_BYPASS_EC_WITH_EBIT_LITTLE 8 Kbytes ASI_ATOMIC_QUAD_LDD_PHYS ASI_ATOMIC_QUAD_LDD_PHYS_LITTLE SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 116: Tlb Replacement Policy

    F.11.10 TLB Replacement Policy Automatic TLB Replacement Rule On an automatic replacement write to the TLB, the MMU picks the entry to write according to the following rules: 1. If the following conditions are satisfied— the new entry maps to an 8-Kbyte or an 4-Mbyte unlocked page and ASI_MCNTRL.fw_fITLB = 0 for IMMU automatic replacement and ASI_MCNTRL.fw_fDTLB = 0 for DMMU automatic replacement —then the replacement is directed to the sTLB (2-way TLB).
  • Page 117 = 1 should be satisfied. Only if this condition is satisfied can the 4-Mbyte sTLB entry be replaced as designated. Otherwise, the stxa instruction is ignored without notification to software. The preceding restriction is SPARC64 V specific. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 118 F. A P P E N D I X Assembly Language Syntax Please refer to Appendix G of Commonality.
  • Page 119 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 120 F. A P P E N D I X Software Considerations Please refer to Appendix H of Commonality.
  • Page 121 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 122 F. A P P E N D I X Extending the SPARC V9 Architecture Please refer to Appendix I of Commonality.
  • Page 123 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 124 F. A P P E N D I X Changes from SPARC V8 to SPARC Please refer to Appendix K of Commonality.
  • Page 125 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 126 F. A P P E N D I X Programming with the Memory Models Please refer to Appendix J of Commonality.
  • Page 127 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 128: Sparc64 V Asi Assignments

    F. A P P E N D I X Address Space Identifiers Every load or store address in a SPARC V9 processor has an 8-bit Address Space Identifier (ASI) appended to the VA. The VA plus the ASI fully specifies the address. For instruction loads and for data loads or stores that do not use the load or store alternate instructions, the ASI is an implicit ASI generated by the hardware.
  • Page 129 ASI_SCRATCH_REG0 ASI_SCRATCH_REG1 ASI_SCRATCH_REG2 ASI_SCRATCH_REG3 ASI_SCRATCH_REG4 ASI_SCRATCH_REG5 ASI_SCRATCH_REG6 ASI_SCRATCH_REG7 –66 (JPS1) — ASI_ALL_FLUSH_L1I –69 (JPS1) — ASI_L2_CTRL ASI_L2_DIAG_TAG_READ -7FFC0 ASI_L2_DIAG_TAG_READ_REG (JPS1) — ASI_ERROR_IDENT (ASI_EIDR) ASI_C_LBSYR0 ASI_C_LBSYR1 ASI_C_BSTW0 ASI_C_BSTW1 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 130: Special Memory Access Asis

    SPARC64 V ASI Assignments (3 of 3) TABLE L-1 Value ASI Name (Suggested Macro Syntax) Type Description Page ASI_C_BSTWBUSY –EE (JPS1) ASI_LBSYR0 ASI_LBSYR1 ASI_BSTW0 ASI_BSTW1 –FF (JPS1) L.3.2 Special Memory Access ASIs Please refer to Section L.3.3 in Commonality. In addition to the ASIs described in Commonality, SPARC64 V supports the ASIs described below.
  • Page 131 2 byte boundary, a SPARC64 V processor behaves as follows: 3 ( 8-byte alignment): no exception related to memory address alignment is generated. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 132: Barrier Assist For Parallel Processing

    n = 2 (4-byte alignment): LDDF_mem_address_not_aligned exception is generated. 1 ( 2-byte alignment): mem_address_not_aligned exception is generated. 2. If the memory address is correctly aligned, SPARC64 V generates a data_access_exception with AFSR.FTYPE = “invalid ASI.” Barrier Assist for Parallel Processing SPARC64 V has a barrier-assist feature that works in concert with the barrier mechanism in the memory system to enable high-speed synchronization among CPUs in the system.
  • Page 133: Asi Registers

    LBSY selected by BL_num and SB_BPU_num is read. SB BPU relative number on the SB. SB_BPU_num BL number in the selected SB BPU. BL_num SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 134 BSTW Control Register (ASI_C_BSTW0, ASI_C_BSTW1) Register Name: , ASI_C_BSTW1 ASI_C_BSTW0 ASI: ASI_C_BSTW0 ASI_C_BSTW1 Supervisor read/write The BSTW control register designates which bit in LBSY is written through ASI_BSTWx. Name Description Valid. When V = 0, BL_num and SB_BPU_num are ignored and a write to ASI_BSTWx is discarded. When V = 1, data in the ASI_BSTWx is written to the selected bit in SB_BPU.
  • Page 135 Write (0 is returned on read) ASI_BSTWx is a write interface to LBSY on the SB. On read, 0 is returned. Name Description Write value. The bit designated by ASI_C_BSTWx is written. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 136: Cache Types

    F. A P P E N D I X Cache Organization This appendix describes SPARC64 V cache organization in the following sections: Cache Types on page 125 Cache Coherency Protocols on page 128 Cache Control/Status Instructions on page 128 Cache Types SPARC64 V has two levels of on-chip caches, with these characteristics: Level-1 cache is split for instruction and data;...
  • Page 137: Level-1 Instruction Cache (L1I Cache)

    Programming Note – This feature is intended to be used by the OBP to facilitate diagnostics procedures. When the OBP uses this feature, it must clear MCNTL.NC_CACHE and invalidate all L1I data by ASI_FLUSH_L1I before it exits. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 138: Level-1 Data Cache (L1D Cache)

    M.1.2 Level-1 Data Cache (L1D Cache) The level-1 data cache is a writeback cache. Its characteristics are shown in TABLE M-2 L1D Cache Characteristics TABLE M-2 Feature Value Size 128 Kbytes Associativity 2-way Line Size 64-byte Indexing Virtually indexed, physically tagged (VIPT) Tag Protection Parity and duplicate Data Protection...
  • Page 139: Cache Coherency Protocols

    Several ASI instructions are defined to manipulate the caches. The following conventions are common to all of the load and store alternate instructions defined in this section: SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 140: Flush Level-1 Instruction Cache (Asi_Flush_L1I)

    1. The opcode of the instructions should be ldda, ldxa, lddfa, stda, stxa, or stdfa. Otherwise, a exception with D-SFSR.FT = 08 data_access_exception (Invalid ASI) is generated. 2. No operand address translation is performed for these instructions. 3. VA<2:0> of all of the operand address should be 0. Otherwise, a exception is generated.
  • Page 141: Level-2 Cache Control Register (Asi_L2_Ctrl)

    M.3.3 L2 Diagnostics Tag Read (ASI_L2_DIAG_TAG_READ) This ASI instruction is a diagnostic read of L2 cache tag, as well as tag 2 of L1I and L1D. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 142: L2 Diagnostics Tag Read Registers (Asi_L2_Diag_Tag_Read_Reg)

    ASI_L2_DIAG_TAG_READ works in concert with ASI_L2_DIAG_TAG_READ_REG. A read to ASI_L2_DIAG_TAG_READ returns 0, with the side effect of setting the tag to ASI_L2_DIAG_TAG_READ_REG0-6. Register Name: ASI_L2_DIAG_TAG ASI: VA<18:6>: Index number of the tag. 0000 –7FFC0 Supervisor read Data 0 is read. M.3.4 L2 Diagnostics Tag Read Registers (ASI_L2_DIAG_TAG_READ_REG)
  • Page 143 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 144: Interrupt Dispatch

    F. A P P E N D I X Interrupt Handling Interrupt handling in SPARC64 V is described in these sections: Interrupt Dispatch on page 133 Interrupt Receive on page 135 Interrupt-Related ASR Registers on page 136 Interrupt Dispatch When a processor wants to dispatch an interrupt to another UPA port, it first sets up the interrupt data registers (ASI_INTR_W data 0-7) with the outgoing interrupt packet data by using ASI instructions.
  • Page 145 . . . Write ASI_INTR_W (data 7) Write ASI_INTR_W (interrupt dispatch) MEMBAR read ASI_INTR_DISPATCH_STATUS Busy? PSTATE.IE (end atomic sequence) Nack? dispatch complete Dispatching an Interrupt FIGURE N-1 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 146: Interrupt Receive

    Interrupt Receive When an interrupt packet is received, eight interrupt data registers are updated with the associated incoming data and the BUSY bit in the ASI_INTR_RECEIVE register is set. If interrupts are enabled (PSTATE.IE = 1), then the processor takes a trap and the interrupt data registers are read by the software to determine the appropriate trap handler.
  • Page 147: Interrupt Global Registers

    SPARC64 V sets a 5-bit physical module ID (MID) value in the SID_L field of the Interrupt Vector Receive Register. The SID_U field always reads as zero. SPARC64 V obtains the interrupt source identifier SID_L from the UPA packet (impl. dep. #247). SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 148: Reset Types

    F. A P P E N D I X Reset, RED_state, and error_state The appendix contains these sections: Reset Types on page 137 RED_state and error_state on page 139 Processor State after Reset and in RED_state on page 141 Reset Types This section describes the four reset types: power-on reset, watchdog reset, externally initiated reset, and software-initiated reset.
  • Page 149: Watchdog Reset (Wdr)

    RSTVaddr + 80 and enter RED_state. If a processor executes an SIR instruction while TL = 5, it enters error_state and ultimately generates a watchdog reset trap. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 150: Red_State And Error_State

    RED_state and error_state illustrates the processor state transition diagram. FIGURE O-1 Fatal Error CPU Fatal Error *** Fatal Error TRAP TRAP@MAXTL WDT1@<MAXTL @<MAXTL-1 SIR@MAXTL WDT1@MAXTL–1 TRAP@<MAXTL WDT1* TRAP@MAXTL–1 WDT2** SIR@<MAXTL WDT1@MAXTL @<MAXTL-1 SIR@<MAXTL ErrorState trans Error TRAP@MAXTL RED = 1 SIR@MAXTL WDT2* error_state**...
  • Page 151: Error_State

    (WDR) and transitions to RED_state. Otherwise, the OPSR (Operating Status Register) specifies the stop on error_state, that is, the processor does not generate a watchdog reset after error_state transition and remains in the error_state. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 152: Cpu Fatal Error State

    O.2.3 CPU Fatal Error state The processor enters CPU fatal error state when a fatal error is detected on the processor. A fatal error is one that breaks the cache coherency or the system data integrity and is not reported as the SDC (small data corruption) error. See Appendix P, Error Handling, for details of the SDC error.
  • Page 153 @ TL = MAX_TL are taken in RED_state. See Section O.1.2, Watchdog Reset (WDR), on page 138 for more details. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 154 ASR State after Reset and in RED_state TABLE O-2 RED_state Name Unknown/Unchanged Unchanged Unknown/Unchanged Unchanged Unknown/Unchanged Unchanged Unchanged Unchanged Unchanged TICK Restart at 0 Unchanged Restart at 0 Unchanged Counter Unchanged Unchanged Unknown/Unchanged Others Unknown/Unchanged Unchanged Always 0 Unchanged Unchanged Unknown/Unchanged Unchanged thers...
  • Page 155 Unknown/Unchanged Unchanged ITLB_DATA_IN — Unknown/Unchanged Unchanged ITLB_DATA_ACCESS — Unknown/Unchanged Unchanged ITLB_TAG_READ — Unknown/Unchanged Unchanged ITLB_DEMAP Unknown/Unchanged Unchanged DMMU_TAG_TARGET Unknown/Unchanged Unchanged PRIMARY_CONTEXT Unknown/Unchanged Unchanged SECONDARY_CONTEXT Unknown/Unchanged Unchanged DMMU_SFSR SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 156 ASI Register State After Reset and in (3 of 3) RED_state TABLE O-3 Name RED_state Unknown/Unchanged Unchanged DMMU_SFAR Unknown/Unchanged Unchanged DMMU_TSB_BASE Unknown/Unchanged Unchanged DMMU_TAG_ACCESS Unknown/Unchanged Unchanged DMMU_VA_WATCHPOINT Unknown/Unchanged Unchanged DMMU_PA_WATCHPOINT Unknown/Unchanged Unchanged DMMU_TSB_PEXT Unknown/Unchanged Unchanged DMMU_TSB_NEXT — Unknown/Unchanged Unchanged DMMU_TSB_8KB_PTR —...
  • Page 157: Operating Status Register (Opsr)

    2. The value of UPA_configuration_register.MCAP field. OPSR can be set so that when error_state is entered, the processor remains halted in error_state instead of generating a (impl. dep. #254). watchdog_reset SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 158: Hardware Power-On Reset Sequence

    O.3.2 Hardware Power-On Reset Sequence To be defined later. O.3.3 Firmware Initialization Sequence To be defined later. Release 1.0, 1 July 2002 F. Chapter O Reset, RED_state, and error_state...
  • Page 159 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 160: Error Classification

    F. A P P E N D I X Error Handling This appendix describes processor behavior to a programmer writing operating system, firmware, and recovery code for SPARC64 V. Section headings differ from those of Appendix P of Commonality. Error Classification On SPARC64 V, an error is classified into one of the following four categories, depending on the degree to which it obstructs program execution: 1.
  • Page 161: Error_State Transition Error

    POST/OBP reset routine, one of the following actions occurs: Whenever possible, the CPU writes an unpredictable value to the target of the damaged instruction and the instruction ends. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 162 Otherwise, an error exception is generated and the damaged instruction is executed as when ASI_ERROR_CONTROL.WEAK_ED = 0 is set. The three types of instruction-obstructing errors are described below. (instruction urgent error) — All of the instruction-obstructing errors except I_UGE (instruction access error) and (data access error).
  • Page 163: Restrainable Error

    Uncorrectable error without direct damage to the currently executing instruction sequence. An error detected in cache line writeback or copyback data is of this type. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 164: Action And Error Control

    Degradation SPARC64 V can isolate an internal hardware resource that generates frequent errors and continue processing without deleterious effect on software during program execution. However, performance is degraded by the resource isolation. This degradation is reported as a restrainable error. The restrainable error can be reported to privileged software by the trap.
  • Page 165: Summary Of Actions Upon Error Detection

    RTE_xx is RTE_CEDG or causes the trap when the RTE_UE. trap is enabled. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 166 Action Upon Detection of an Error (2 of 4) TABLE P-2 Error State Transition Fatal Error (FE) Error (EE) Urgent Error (UGE) Restrainable Error (RE) Action upon the 1. CPU enters 1. CPU enters Detection of I_UGE Ideal specification error detection CPU fatal 1.
  • Page 167 RETRY DONE A_UGE None. The instruction pointed to by caused the error. Register that I_UGE A_UGE ASI_STCHG_ ASI_STCHG_ ASI_AFSR indicates the ERROR_INFO ERROR_INFO ASI_UGESR error ASI_ISFSR ASI_DSFSR SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 168: Extent Of Automatic Source Data Correction For Correctable Error

    Action Upon Detection of an Error (4 of 4) TABLE P-2 Error State Transition Fatal Error (FE) Error (EE) Urgent Error (UGE) Restrainable Error (RE) Number of All FEs are All EEs are All restrainable errors Single-ADE trap errors detected and detected and detected and accumulated s and...
  • Page 169 ECC are replaced in the data by error marking, as listed in TABLE P-4 Format of Error-Marked Data TABLE P-4 Data/ECC Value data Error bit. The value is unpredictable. 62:56 0 (7 bits). 55:42 ERROR_MARK_ID (14 bits). SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 170 Format of Error-Marked Data TABLE P-4 Data/ECC Value 41:36 0 (6 bits). Error bit. The value is unpredictable. 34:23 0 (12 bits). Error bit. The value is unpredictable. 21:14 0 (8 bits). 13:0 ERROR_MARK_ID (14 bits). The pattern indicates 3-bit error in bits 63, 35, and 22, that is, the pattern causing the 7F syndrome.
  • Page 171 ERROR_MARK_ID. On SPARC64 V, error marking is not applied to incoming interrupt packet data. On SPARC64 IV, error marking is applied even for incoming interrupt packet data. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 172: Asi_Eidr

    P.2.5 ASI_EIDR The ASI_EIDR register designates the source ID in the ERROR_MARK_ID of the CPU. Register name: ASI_EIDR ASI: Error checking: Parity. Format & function: TABLE P-8 Bit Description ASI_EIDR TABLE P-8 Name Description 63:14 Reserved Always 0. 13:0 ERROR_MARK_ID for the error caused by the CPU. ERROR_MARK_ID P.2.6 Control of Error Action (ASI_ERROR_CONTROL)
  • Page 173 UGE_HANDLER is set to 1. async_data_error When a RETRY or DONE instruction is completed, UGE_HANDLER is set to 0. Other Reserved Always reads as 0. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 174: Fatal Error And Error_State Transition Error

    Fatal Error and error_state Transition Error P.3.1 ASI_STCHG_ERROR_INFO The ASI_STCHG_ERROR_INFO register stores detected FATAL error and error_state transition error information, for access by OBP (Open Boot PROM) software. Register name: ASI_STCHG_ERROR_INFO ASI: Error checking: None Format & function: TABLE P-10 Initial value at reset: Hard POR: All fields are set to 0.
  • Page 175: Fatal Error Types

    Current SPARC64 V implementation When hardware detects an error_state transition error other than those described above, it causes a watchdog reset without setting any EE_xxxx bits in ASI_STCHG_ERROR_INFO. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 176: Urgent Error

    Ideal specification (not implemented) The EE_OTHER bit is specified in ASI_STCHG_ERROR_INFO bit 14. When hardware detects error_state transition errors other than those described above, it sets ASI_STCHG_ERROR_INFO.EE_OTHER = 1. Urgent Error This section presents details about urgent errors: status monitoring, actions, and end-methods.
  • Page 177 Uncorrectable error in any floating-point register or in the FPRS, FSR, or GSR IUG_%F register. Uncorrectable error in any general-purpose (integer) register, or in the Y, CCR, IUG_%R or ASI register. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 178 Bit Description (3 of 4) ASI_UGESR TABLE P-11 Name Description System data corruption. Indicates the occurrence of the following system data AUG_SDC corruption: Small data corruption: Data in the cacheable area with an unpredictable address is destroyed. The destroyed area is some number of 64-byte blocks. Invalid physical address usage by software: On SPARC64 V, the following invalid physical address usage by software causes system data corruption: •...
  • Page 179 When ASI_ERROR_CONTROL.UGE_HANDLER = 1 and , and/or I_UGEs are detected, a multiple- trap is generated. 2. State change, trap target address calculation, and TL manipulation. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 180 The following actions are executed in this order: a. State transition if (TL = MAXTL), the CPU enters error_state and abandons the trap; else if (CPU is in execution state && (TL = MAXTL 1)), then the CPU enters RED_state. b.
  • Page 181 Precise Retryable but not precise (not included in JPS1) Not retryable (not included in JPS1) Upon a single-ADE trap, the trapped instruction end-method is indicated in ASI_UGESR.INSTEND. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 182 defines each instruction end-method after an trap. TABLE P-14 Instruction End-Method After Exception async_data_error TABLE P-14 Precise Retryable But Not Precise Not Retryable Instructions executed after Ended (Committed). the last , or The instructions without complete as defined in the architecture. The trap and before the trapped instruction with was unpredictable value to its output (destination register or,...
  • Page 183 DTLB; /* A locked fDTLB entry with uncorrectable error is not removed by this operation. A locked fDTLB entry with UE never detects its tag match or SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 184: Instruction Access Errors

    causes the data_access_error trap when its tag matches at the DTLB reference for address translation. */ if (ASI_UGESR.IUG_ITLB == 1) { execute demap_all for ITLB; /* A locked fITLB entry with uncorrectable error is not removed by this operation. A locked fITLB entry with UE never detects its tag match or causes the data access error trap when its tag matches at the ITLB reference for address translation.
  • Page 185: Restrainable Errors

    ASI_AFAR_D1 and ASI_AFAR_D1 is unchanged. column — Indicates the ASI_AFAR_U2 recording priority for each error Prio_U2 shown in the row as follows: TABLE P-15 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 186 If the column for the error shown in the table row is blank, the error is Prio_U2 never recorded into ASI_AFAR_U2. Otherwise, the column for the error shown in the table row indicates Prio_U2 the ASI_AFAR_U2 recording priority, as follows. Let P_U2 be the Prio_U2 column value for the error .
  • Page 187 The doubleword containing a raw in the outgoing data and that in D1 cache are marked with ERROR_MARK_ID = ASI_EIDR Other Reserved Always reads as 0; writes are ignored. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 188: Asi_Async_Fault_Addr_D1

    P.7.2 ASI_ASYNC_FAULT_ADDR_D1 Register name: ASI_ASYNC_FAULT_ADDR_D1 (ASI_AFAR_D1) ASI: Error checking: Parity Format & function: TABLE P-16 Initial value at reset: Hard POR: All fields in ASI_AFAR_D1 are set to 0. Other reset: Value in ASI_AFAR_D1 is unchanged. Update: When a new restrainable error is detected, ASI_AFAR_D1 is updated as defined in Section P.7.1 in the notes on the AFSR Prio_D1 column of TABLE P-15...
  • Page 189: Asi_Async_Fault_Addr_U2

    Syndrome of incoming data at L2$ fill. When ASI_AFAR_U2.CONTENTS SYNDROME indicates CE_INCOMED or UE_L2$FILL, this field indicates the syndrome of the doubleword with error incoming from UPA bus. Otherwise, this field indicates the unpredictable value. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 190: Expected Software Handling Of Restrainable Errors

    ASI_ASYNC_FAULT_ADDR_U2 (ASI_AFAR_U2) Register Bit Description (Continued) TABLE P-17 Name Description 42:3 Physical address bit 42:3. Contains the value indicated by PA_BIT42_3 ASI_AFAR_U2.CONTENTS, as shown below: Error Name Contents of PA_BIT42_3 ASI_AFAR_U2.CONTENTS The physical address of the CE_INCOMED doubleword with the error. UE_RAW_L2$FILL The physical address of the doubleword with the error.
  • Page 191 This situation may occur at the condition described in the on page 154 TABLE P-2 (see the third row, last column, and “Deviation from the ideal specification”). SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 192: Handling Of Internal Register Errors

    Handling of Internal Register Errors This section describes error handling for the following: Most registers ASR registers ASI registers P.8.1 Register Error Handling (Excluding ASRs and ASI Registers) The terminology used in is defined as follows: TABLE P-18 Column Term Meaning Error Detect InstAccess...
  • Page 193: Asr Error Handling

    Error Protect Error Detect Condition Error Type Correction RW Parity InstAccess IUG_%R — RW Parity Always IUG_%R trap, W RW Parity Always IUG_%R trap, W RW None — — — TICK SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 194: Asi Register Error Handling

    ASR Error Handling (Continued) TABLE P-19 Number Register Name Error Protect Error Detect Condition Error Type Correction Parity Always trap IUG_PSTATE RW Parity Always IUG_%F trap, W FPRS — 8-15 — RW None — — — RW None — — —...
  • Page 195 ASI_INTR_RECEIVE.BUSY = 0. BV interface Uncorrected error in the Barrier Variable transfer interface between the processor and the memory system is checked during the AUG_always period. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 196 (3 of 3) Column Term Meaning Error Type error_state transition error. error_state The error is indicated by ASI_UGESR.IAUG_xxxx = 1, and the error class is AUG_xxxx autonomous urgent error. The error is indicated by ASI_UGESR.IAUG_xxxx = 1, and the error class is I(A) UG_xxxx instruction urgent error.
  • Page 197 LDXA #D I(A)UG_TSBCTXT Use for TLB (I)AUG_TSBCTXT always Parity = P_CONTEXT IAUG_TSBCTXT SECONDARY_CONTEXT None — — — DMMU_SFSR Parity IAUG_CRE DMMU_SFAR LDXA Parity LDXA #D I(A)UG_TSBCTXT DMMU_TSB_BASE SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 198 Handling of ASI Register Errors (Continued) TABLE P-20 Error Error Detect Register Name Protect Condition Error Type Correction Parity LDXA #D W (WotherD) IUG_TSBP DMMU_TAG_ACCESS Parity Enabled (I)AUG_CRE DMMU_VA_WATCHPOINT I(A)UG_CRE LDXA Parity Enabled (I)AUG_CRE DMMU_PA_WATCHPOINT I(A)UG_CRE LDXA Parity = DTSB_BASE I(A)UG_TSBCTXT DMMU_TSB_PEXT Parity...
  • Page 199: Cache Error Handling

    U2 (unified level 2) cache. The D1 cache tags, the D1 cache tags copy, the I1 cache tags, and the I1 cache tags copy are each protected by parity. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 200 When a parity error is detected in a D1 cache tag entry or in a D1 cache tag copy entry, hardware automatically corrects the error by copying the correct tag entry from the other copy of the tag entry. If the error can be corrected in this way, program execution is unaffected.
  • Page 201: Handling Of An I1 Cache Data Error

    When a correctable error is detected in D1 cache data, the data is corrected automatically by hardware. There is no direct report to software for a D1 cache correctable error. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 202 Marked Uncorrectable Error in D1 Cache Data When a marked uncorrectable error ( ) in D1 cache data is detected during the D1 cache line writeback to the U2 cache, the D1 cache data and its ECC are written to the target U2 cache data and its ECC without modification.
  • Page 203: Handling Of A U2 Cache Data Error

    UPA, or writeback to UPA, then error marking is applied for the doubleword with the raw , using ERROR_MARK_ID = ASI_EIDR. Both the SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 204: Automatic Way Reduction Of I1 Cache, D1 Cache, And U2 Cache

    doubleword and its ECC in the read data and those in the source U2 cache line are changed to marked data. The restrainable error ASI_AFSR.UE_RAW_L2$INSD detected. Implementation Note – SPARC64 V detects only on ASI_AFSR.UE_FAW_L2$INSD writeback. P.9.5 Automatic Way Reduction of I1 Cache, D1 Cache, and U2 Cache When frequent errors occur in the I1, D1, or U2 cache, hardware automatically detects that condition and reduces the way, maintaining cache consistency.
  • Page 205 U2 cache way. The U2 cache data is invalidated to retain system consistency. The restrainable error is reported to software, even ASI_AFSR.DG_L1$U2$STLB though the available U2 cache configuration is not changed as a result of the error. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 206: Tlb Error Handling

    2. Otherwise: All entries in available U2 cache ways, including way W, are invalidated to retain system consistency. Way W becomes unavailable and is never refilled. The restrainable error is reported to software. ASI_AFSR.DG_L1$U2$STLB P.10 TLB Error Handling This section describes how TLB entry errors and sTLB way reduction are handled. P.10.1 Handling of TLB Entry Errors Error protection and error detection in TLB entries are described in...
  • Page 207: Automatic Way Reduction Of Stlb

    Hardware counts TLB entry parity error occurrences for each sITLB way and sDTLB way. If the error count per unit of time exceeds a predefined threshold, hardware recognizes an sTLB way reduction condition. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 208: Handling Of Extended Upa Bus Interface Error

    sTLB Way Reduction When a way reduction condition is recognized for the sTLB way W (W = 0 or 1), hardware executes the following way reduction procedures: 1. When only one way in sTLB is active because of previous way reductions: The previously reduced way is reactivated.
  • Page 209 ) coming from the extended UPA bus depends on whether the access was to cacheable or noncacheable data and whether the access was an instruction fetch, load, or store instruction, as follows: SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 210 Incoming noncacheable data fetched by an instruction fetch. When a detected in such data, an with marked is detected at the instruction_access_error time the fetched instruction is executed. Incoming noncacheable data loaded by a load instruction. When the detected in such data, a with marked is detected at the time data_access_error...
  • Page 211 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 212: Performance Monitor Overview

    F. A P P E N D I X Performance Instrumentation This appendix describes and specifies performance monitors that have been implemented in the SPARC64 V processor. The appendix contains these sections: Performance Monitor Overview on page 201 Performance Monitor Description on page 203 Instruction Statistics on page 204 Trap-Related Statistics on page 206 MMU Event Counters on page 207...
  • Page 213 /* disable counts */ pcr.st = 0x0; /* disable counts */ pcr.ulro = 0x1; /* enable sl/su read-only */ pcr.ovro = 0x1; /* do not modify overflow bits */ SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 214: Performance Monitor Description

    for(i=0; i<=pcr.nc; i++) { /* assume rest of pcr data has been preserved */ pcr.sc = i; wr_pcr(pcr); pic = rd_pic(); picl[i] = pic.picl; picu[i] = pic.picu; Performance Monitor Description The performance monitors can be divided into the following groups: 1.
  • Page 215: Instruction Statistics

    Counts the cycles when the performance monitor is enabled. This counter is similar to the %tick register but can separate user cycles from system cycles, based on PCR.UT and PCR.ST selection. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 216 Instruction Count (instruction_counts) Counter Encoding 000001 Counts the number of committed instructions. For user or system mode counts, this counter is exact. Combined with the cycle_counts, it provides instructions per cycle. IPC = instruction_counts / cycle_counts If Instruction_counts and cycle_counts are both collected for user or system mode, IPC in user or system mode can be derived.
  • Page 217: Trap-Related Statistics

    Encoding 010110 Counts the occurrences of spill_ _normal spill_ _other Fill Trap Count (trap_fill) Counter picu2 Encoding 010110 Count the occurrences of fill_ _normal fill_ _other SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 218: Mmu Event Counters

    Software Instruction Trap (trap_trap_inst) Counter picl2 Encoding 010110 Counts the occurrences of Tcc instructions. Instruction MMU Miss Trap (trap_IMMU_miss) Counter picu3 Encoding 010110 Counts the occurrences of fast_instruction_access_MMU_miss Data MMU Miss Trap (trap_DMMU_miss) Counter picl3 Encoding 010110 Counts the occurrences of fast_data_instruction_access_MMU_miss Q.2.3 MMU Event Counters...
  • Page 219: Cache Event Counters

    Encoding 110000 Counts the number of cycles from the occurrence of an L2 cache miss to data returned, caused by both software prefetch and hardware prefetch access. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 220 L2 Cache Miss Count by Demand Access (sx_miss_count_dm) Counter picu1 Encoding 110000 Counts the occurrences of L2 cache miss by demand access. L2 Cache Miss Count by Prefetch (sx_miss_count_pf) Counter picl1 Encoding 110000 Counts the occurrences of L2 cache miss by both software prefetch and hardware prefetch access.
  • Page 221: Upa Event Counters

    Counter picl2 Encoding 110001 Counts the number of bus-busy cycles of the UPA data bus, in units of UPA bus clocks, not in units of CPU clocks. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 222: Miscellaneous Counters

    Q.2.6 Miscellaneous Counters Barrier-Assist ASI Read Count (asi_rd_bar) Counter picu3 Encoding 110001 Counts the number of read accesses to the barrier-assist ASI registers. Barrier-Assist ASI Write Count (asi_wr_bar) Counter picl3 Encoding 110001 Counts the number of write accesses to the barrier-assist ASI registers. Release 1.0, 1 July 2002 F.
  • Page 223 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 224: Mapping Of The Cpu's Upa Port Slave Area

    F. A P P E N D I X UPA Programmer ’s Model This chapter describes the programmers model of the UPA interface of the SPARC64 V. The registers for the UPA interface and the access method for those registers are described. The appendix contains the following sections: Mapping of the CPU’s UPA Port Slave Area on page 213 UPA PortID Register on page 214 UPA Config Register on page 215...
  • Page 225: Upa Portid Register

    P_REQ transaction request packets the UPA slave can receive. Set to 1, since only one incoming P_REQ to the UPC can be outstanding at a time. SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 226: Upa Config Register

    UPA PortID Register Fields (Continued) TABLE R-2 Field Description 20:16 UPACAP<4:0>. Indicates the UPA module capability type, as UPACAP follows: UPACAP<4> Set; CPU is an interrupt handler. UPACAP<3> Set; CPU is an interrupter. UPACAP<2> Clear; CPU does not use UPA Slave_Int_L signal. UPACAP<1>...
  • Page 227 Specify the ratio between CPU clock and UPA’ clock. CLK_MODE 0000 – 0011 : Reserved 0100 0101 0110 0111 1000 1001 1010 10:1 1011 11:1 1100 12:1 1101 13:1 1110 14:1 1111 15:1 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 228 UPA Config Register Description (Continued) TABLE R-3 Bits Field Description 29:23 Processor Configuration. Separated into PCON<6:4> and PCON<3:0>. PCON PCON<6:4> (UPA_CONFIG<29:27>) represents the size of class 1 request queue in the System Controller (SC). – 010 1, but should not be specified for the extension –...
  • Page 229 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 230: S. Summary Of Differences Between Sparc64 V And Ultrasparc-Iii

    F. A P P E N D I X Summary of Differences between SPARC64 V and UltraSPARC-III The following table summarizes differences between SPARC64 V and UltraSPARC-III ISAs. This list is a summary, not an exhaustive list. SPARC64 V and UltraSPARC-III Differences (1 of 3) TABLE T-1 SPARC64 V...
  • Page 231 ASIs 4B , 4E , 74 , 75 , 76 L.3.2 cache diagnostic access. and 7E support control over the E-cache. Many differences. Many differences. P.4.2 ASI_AFSR SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 232 SPARC64 V and UltraSPARC-III Differences (3 of 3) TABLE T-1 SPARC64 V UltraSPARC- Feature SPARC64 V Page UltraSPARC-III III Section Error status ASI 4C (ASI_UGESR): Not implemented. — SPARC64 V implements an error status register to indicate where an error was detected. Error Control ASI 4C (ASI_ECR):...
  • Page 233 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 234: Bibliography

    F. C H A P T E R Bibliography General References Please refer to Bibliography in Commonality.
  • Page 235 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 236: Index

    F. C H A P T E R Index A_UGE categories152 error detection action155 error detection mask154 specification of151 address mask (AM) field of PSTATE register49 address space identifier (ASI) complete list117 conditions causing168 end-method170 registers written for update/validation169 software handling171 state transition169 AFSR FTYPE field120...
  • Page 237 ASI_DTLB_TAG_ACCESS195 ASI_ECR161 UGE_HANDLER155 ASI_EIDR153 ASI_ERROR_CONTROL153 UGE_HANDLER168 update after ADE170 WEAK_ED150 ASI_FLUSH_L1I126 ASI_IESR118 ASI_IMMU_SFSR153 ASI_IMMU_TAG_ACCESS166 ASI_IMMU_TAG_TARGET166 ASI_IMMU_TSB_64KB_PTR166 ASI_IMMU_TSB_8KB_PTR166 ASI_IMMU_TSB_BASE166 ASI_IMMU_TSB_PEXT166 ASI_IMMU_TSB_SEXT166 ASI_INT_ERROR_CONTROL118 ASI_INT_ERROR_RECOVERY118 ASI_INT_ERROR_STATUS118 ASI_INTR_DISPATCH_STATUS134 ASI_INTR_DISPATCH_W166 ASI_INTR_R135 ASI_INTR_RECEIVE135 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 238 ASI_INTR_W133 ASI_ITLB_DATA_ACCESS196 ASI_ITLB_TAG_ACCESS196 ASI_L2_CTRL130 ASI_L2_DIAG_TAG131 ASI_L2_DIAG_TAG_READ_REG131 ASI_L3_DIAG_DATA0_REG118 ASI_L3_DIAG_DATA1_REG118 ASI_LBSYR0124 ASI_LBSYR1124 ASI_MCNTL92 JPS1_TSBP88 ASI_MEMORY_CONTROL_REG118 ASI_NUCLEUS57 ASI_NUCLEUS_LITTLE57 ASI_PA_WATCH_POINT166 ASI_PARALLEL_BARRIER166 ASI_PHYS_BYPASS_EC_WITH_E_BIT127 ASI_PHYS_BYPASS_EC_WITH_E_BIT_LITTLE127 ASI_PHYS_BYPASS_WITH_EBIT26 ASI_PRIMARY57 ASI_PRIMARY_AS_IF_USER57 ASI_PRIMARY_AS_IF_USER_LITTLE57 ASI_PRIMARY_CONTEXT166 ASI_PRIMARY_LITTLE57 ASI_SCRATCH120 ASI_SECONDARY57 ASI_SECONDARY_AS_IF_USER57 ASI_SECONDARY_AS_IF_USER_LITTLE57 ASI_SECONDARY_CONTEXT166 ASI_SECONDARY_LITTLE57 ASI_SERIAL_ID119 ASI_STCHG_ERROR_INFO153 ASI_UGESR165 IUG_DTLB195 ASI_UPA_CONFIGURATION_REGISTER118 ASI_URGENT_ERROR_STATUS153 ASI_VA_WATCH_POINT166 ASRs20 exception25 async_data_error ASYNC_FAULT_STATUS register186 asynchronous error17...
  • Page 239 – event counting208 instruction characteristics126 data protection190 description7 error handling190 fetched9 flushing/invalidation129 invalidation125 way reduction193 level-1 characteristics125 tag 2 read130 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 240 level-2 characteristics125 control register130 tag read130 unified127 use2 snooping140 synchronizing42 unified characteristics127 description8 CALL instruction24 CANRESTORE register166 CANSAVE register166 CASA instruction37 CASXA instruction37 exception37 catastrophic_error correction157 counting in D1 cache data193 in D1 cache data190 detection175 effect on CPU152 permanent180 in U2 cache tag189 CLEANWIN register75 CLEAR_SOFTINT register183...
  • Page 241 VM (VA data watchpoint mask) field23 VR/VW (VA data watchpoint enable) fields23 WEAK_SPCA field23 deferred trap37 deferred-trap queue floating-point (FQ)17 integer unit (IU)11 denormal operands18 results18 DG_L1$L2$STLB error194 DG_L1$U2$STLB error195 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 242 dispatch (instruction)9 disrupting traps17 distribution nonspeculative10 speculative11 DMMU access bypassing104 disabled91 internal register (ASI_MCNTL)92 registers accessed92 Synchronous Fault Status Register97 Tag Access Register90 DMMU_DEMAP register187 DMMU_PA_WATCHPOINT register187 DMMU_SFAR register186 DMMU_SFSR register186 DMMU_TAG_ACCESS register187 DMMU_TAG_TARGET register186 DMMU_TSB_64KB_PTR register187 DMMU_TSB_8KB_PTR register187 DMMU_TSB_BASE register186 DMMU_TSB_DIRECT_PTR register187 DMMU_TSB_NEXT register187 DMMU_TSB_PEXT register187...
  • Page 243 U2 cache tag189 uncorrectable189 D1 cache data191 without direct damage152 urgent150 ERROR_CONTROL register186 ERROR_MARK_ID158 error_state36 error_state transition error164 exceptions catastrophic37 data_access_error data_access_protection data_breakpoint fp_exception_ieee_754 fp_exception_other illegal_instruction LDDF_mem_address_not_aligned mem_address_not_aligned persistence38 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 244 privileged_action – statistics monitoring206 unfinished_FPop execute_state140 executed, definition9 execution EU (execution unit)6 out-of-order25 speculative25 (XIR)138 externally_initiated_reset exception90 fast_data_access_MMU_miss exception90 fast_data_access_protection exception207 fast_data_instruction_access_MMU_miss exception46 fast_instruction_access_MMU_miss fatal error behavior of CPU150 cache tag189 definition149 detection163 types164 U2 cache tag189 fDTLB77 fe_other164 fe_u2tag_uncorrected_error164 fe_upa_addr_uncorrected_error164 fetched, definition9 exception206...
  • Page 245 GSR register183 high-speed synchronization121 I_UGE definition151 error detection action155 error detection mask154 type150 error detection action155 error detection mask154 reporting151 IEEE Std 754-198518 IIU_INST_TRAP register46 exception24 illegal_instruction SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 246 IMMU internal register (ASI_MCNTL)92 registers accessed92 Synchronous Fault Status Register97 IMMU_DEMAP register186 IMMU_SFSR register186 IMMU_TAG_ACCESS register186 IMMU_TAG_TARGET register186 IMMU_TSB_64KB_PTR register186 IMMU_TSB_8KB_PTR register186 IMMU_TSB_BASE register186 IMMU_TSB_NEXT register186 IMMU_TSB_PEXT register186 IMPDEP1 instruction30 IMPDEP2 instruction30 IMPDEP2B instruction28 IMPDEPn instructions49 impl field of VER register18 implementation number (impl) field of VER register71 initiated, definition9 instruction...
  • Page 247 UltraSPARC III221 format97 FT field99 update policy100 issue unit9 issued (instruction)9 issue-stalling instruction instructions issue-stalling10 ITLB_DATA_ACCESS register186 ITLB_DATA_IN register186 ITLB_TAG_READ register186 JEDEC manufacturer code20 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 248 JMPL instruction29 JPS1_TSBP mode93 JTAG command91 LBSY control register122 LDD instruction37 LDDA instruction37 exception80 LDDF_mem_address_not_aligned LDDFA instruction80 exception46 LDQF_mem_address_not_aligned LDSTUB instruction37 LDSTUBA instruction102 LDXA instruction178 load quadword atomic54 LoadLoad MEMBAR relationship56 load-store instructions compare and swap37 D1 cache data errors191 memory model47 LoadStore MEMBAR relationship56 Lookaside MEMBAR relationship56...
  • Page 249 Operating Status Register (OPSR)37 OTHERWIN register75 out-of-order execution25 panic process152 parallel barrier assist187 parity error counting in D1 cache193 D1 cache tag189 fDTLB lookup91 I1 cache data190 I1 cache tag189 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 250 partial ordering, specification56 partial store instruction UPA transaction57 watchpoint exceptions57 partial store instructions120 partial store order (PSO) memory model41 PC register169 accessibility20 counter events, selection202 error handling183 NC field21 OVF field21 OVRO field21 PRIV field20 SC field21 SL field202 ST field204 SU field202 UT field204 performance monitor...
  • Page 251 XIR138 entry trap17 processor states140 restricted environment36 setting of PSTATE.RED20 trap vector36 trap vector address (RSTVaddr)74 registers BSTW busy status123 BSTW control123 clean windows (CLEANWIN)75 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 252 clock-tick (TICK)73 current window pointer (CWP)75 Data Cache Unit Control (DCUCR)23 LBSY control122 other windows (OTHERWIN)75 privileged19 renaming10 restorable windows (CANRESTORE)75 savable windows (CANSAVE)75 relaxed memory order (RMO) memory model41 reservation station11 reserved fields in instructions45 reset (XIR)138 externally_initiated_reset (POR)72 power_on_reset (SIR)138 software_initiated_reset...
  • Page 253 STXA instruction ASI read method178 stxa instruction ASI designation105 virtual address designation105 superscalar11 SWAP instruction37 SWAPA instruction102 sync (machine)11 Sync MEMBAR relationship56 synchronizing caches42 syncing instruction11 system controller122 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...
  • Page 254 Tag Access Register96 Tcc instruction, counting207 TICK register19 TICK_COMPARE register183 TL register138 CP field126 data characteristics77 in TLB organization85 data access address95 Data Access/Data In Register96 index95 instruction characteristics77 in TLB organization85 main10 multiple hit detection86 replacement algorithm93 TNP register166 total store order (TSO) memory model41 TPC register166 transition error150...
  • Page 255 (ver) field of FSR register71 watchdog timeout164 (WDR)37 watchdog_reset watchpoint exception on block load-store48 on partial store instructions57 quad-load physical instruction55 WDR reset155 writeback cache127 WRPCR instruction20 WRPR instruction140 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002...