Storage Unit (Su) - Fujitsu SPARC JPS1 Implementation Supplement Manual

TABLE 1-2
Name
Interface registers
Two integer execution pipelines
(EXA, EXB)
Two floating-point and graphics
execution pipelines (FLA, FLB)
Two virtual address adders for
memory access pipeline (EAGA,
EAGB)
1.3.4

Storage Unit (SU)

The SU handles all sourcing and sinking of data for load and store instructions.
TABLE 1-3
TABLE 1-3
Name
Instruction level-1 cache
Data level-1 cache
Instruction Translation
Buffer
Data Translation Buffer
Store queue
Release 1.0, 1 July 2002
Execution Unit Major Blocks (Continued)
Description
Input/output registers to other units.
64-bit ALU and shifters.
Each floating-point execution pipeline can execute floating
point multiply, floating point add/sub, floating-point
multiply and add, floating point div/sqrt, and floating-
point graphics instruction.
Two 64-bit virtual addresses for load/store.
describes the SU major blocks.
Storage Unit Major Blocks
Description
128-Kbyte, 2-way associative, 64-byte line; provides low latency
instruction source
128-Kbyte, 2-way associative, 64-byte line, writeback; provides
the low latency data source for loads and stores.
1024 entries, 2-way associative TLB for 8-Kbyte pages,
1024 entries, 2-way associative TLB for 4-Mbyte pages
32 entries, fully associative TLB for unlocked 64-Kbyte, 512-
Kbyte, 4-Mbyte
1024 entries, 2-way associative TLB for 8-Kbyte pages,
1024 entries, 2-way associative TLB for 4-Mbyte pages
32 entries, fully associative TLB for unlocked 64-Kbyte, 512-
Kbyte, 4-Mbyte
Decouples the pipeline from the latency of store operations.
Allows the pipeline to continue flowing while the store waits for
data, and eventually writes into the data level 1 cache.
1. Unloced 4-Mbyte page entry is stored either in 2-way associative TLB or fully associative
TLB exclusively, depending on the setting.
1
pages and locked pages in all sizes.
1
pages and locked pages in all sizes.
F. Chapter 1
1
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1
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Overview 7