Fujitsu SPARC JPS1 Implementation Supplement Manual page 7

D. Formal Specification of the Memory Models 81
E. Opcode Maps 83
F. Memory Management Unit 85
Virtual Address Translation 85
Translation Table Entry (TTE) 86
Faults and Traps 89
Reset, Disable, and RED_state Behavior 91
Internal Registers and ASI operations 92
MMU Bypass 104
G. Assembly Language Syntax 107
H. Software Considerations 109
I. Extending the SPARC V9 Architecture 111
J. Changes from SPARC V8 to SPARC V9 113
K. Programming with the Memory Models 115
L. Address Space Identifiers 117
SPARC64 V ASI Assignments 117
Barrier Assist for Parallel Processing 121
M. Cache Organization 125
Cache Types 125
iv SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
TSB Organization 88
TSB Pointer Formation 88
Accessing MMU Registers 92
I/D TLB Data In, Data Access, and Tag Read Registers 93
I/D TSB Extension Registers 97
I/D Synchronous Fault Status Registers (I-SFSR, D-SFSR) 97
TLB Replacement Policy 105
Special Memory Access ASIs 119
Interface Definition 121
ASI Registers 122
Level-1 Instruction Cache (L1I Cache) 126