Cache Event Counters - Fujitsu SPARC JPS1 Implementation Supplement Manual

Q.2.4

Cache Event Counters

I1 Cache Miss Count (if_r_iu_req_mi_go)
Counter
Encoding
Counts the occurrences of I1 cache misses.
D1 Cache Miss Count (op_r_iu_req_mi_go)
Counter
Encoding
Counts the occurrences of D1 cache misses.
I1 Cache Miss Latency (if_wait_all)
Counter
Encoding
Counts the total latency of I1 cache misses.
D1 Cache Miss Latency (op_wait_all)
Counter
Encoding
Counts the total latency of D1 cache misses.
L2 Cache Miss Wait Cycle by Demand Access
(sx_miss_wait_dm)
Counter
Encoding
Counts the number of cycles from the occurrence of an L2 cache miss to data
returned, caused by demand access.
L2 Cache Miss Wait Cycle by Prefetch (sx_miss_wait_pf)
Counter
Encoding
Counts the number of cycles from the occurrence of an L2 cache miss to data
returned, caused by both software prefetch and hardware prefetch access.
208 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
picu2
100000
2
picl2
100000
2
picu3
100000
2
picl3
100000
2
picu0
110000
2
picl0
110000
2