Floating-Point Multiply-Add/Subtract - Fujitsu SPARC JPS1 Implementation Supplement Manual

A.24.1

Floating-Point Multiply-Add/Subtract

SPARC64 V uses IMPDEP2B opcode space to encode the Floating-Point Multiply
Add/Subtract instructions.
Opcode
FMADDs
FMADDd
FMSUBs
FMSUBd
FNMADDs
FNMADDd
FNMSUBs
FNMSUBd
† 11 is reserved for quad.
Format (5)
10 rd
31 30 29 25
Operation
Multiply-Add
Multiply-Subtract
Negative Multiply-Subtract
Negative Multiple-Add
Assembly Language Syntax
fmadds
fmaddd
fmsubs
fmsubd
fnmadds
fnmaddd
fnmsubs
fnmsubd
50 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
Variation Size†
00 01
00 10
01 01
01 10
11 01
11 10
10 01
10 10
110111
24 19 18
freg , freg , freg
rs1 rs2
freg , freg , freg
rs1 rs2
freg , freg , freg
rs1 rs2
freg , freg , freg
rs1 rs2
freg , freg , freg
rs1 rs2
freg , freg , freg
rs1 rs2
freg , freg , freg
rs1 rs2
freg , freg , freg
rs1 rs2
Operation
Multiply-Add Single
Multiply-Add Double
Multiply-Subtract Single
Multiply-Subtract Double
Negative Multiply-Add Single
Negative Multiply-Add Double
Negative Multiply-Subtract Single
Negative Multiply-Subtract Double
rs1 rs3
14 13
Implementation
rd rs1 rs2 rs3
rd rs1 rs2 rs3
( )
rd rs1 rs2 rs3
( )
rd rs1 rs2 rs3
, freg
rs3 rd
, freg
rs3 rd
, freg
rs3 rd
, freg
rs3 rd
, freg
rs3 rd
, freg
rs3 rd
, freg
rs3 rd
, freg
rs3 rd
var size rs2
9 8 7 6 5 4 0