Fujitsu SPARC JPS1 Implementation Supplement Manual page 86

TABLE C-1
Nbr
119
120
121
122
123
124
125
126
127–201 Reserved.
202
203
204
205
Release 1.0, 1 July 2002
SPARC64 V Implementation Dependencies (6 of 11)
SPARC64 V Implementation Notes
Unimplemented values for PSTATE.MM
Writing 11 into PSTATE.MM causes the machine to use the TSO memory
2
model. However, the encoding 11
of SPARC64 V may use this encoding for a new memory model.
Coherence and atomicity of memory operations
Although SPARC64 V implements the UPA-based cache coherency
mechanism, this dependency is beyond the scope of this publication. It
should be defined in a system that uses
Implementation-dependent memory model
SPARC64 V implements TSO, PSO, and RMO memory models. See
Chapter 8, Memory Models, for details.
Accesses to pages with the E (Volatile) bit of their MMU page table entry set
are also made in program order.
FLUSH latency
Since the FLUSH instruction synchronizes the processor, its total latency
varies depending on many portions of the SPARC64 V processor 's state.
Assuming that all prior instructions are completed, the latency of FLUSH is
18 processor cycles
.
Input / output (I/O) semantics
This dependency is beyond the scope of this publication. It should be
defined in a system that uses
Implicit ASI when TL > 0
See Section 5.1.7 of Commonality for details.
Address masking
When PSTATE.AM = 1,
the PC when transmitting it to the destination register.
Register Windows State Registers width
SPARC64 V
NWINDOWS for
the following registers: CWP, CANSAVE, CANRESTORE, OTHERWIN. If an
attempt is made to write a value greater than NWINDOWS
registers, the extraneous upper bits are discarded. The CLEANWIN register
contains 3 bits.
trap
fast_ECC_error
fast_ECC_error trap is not implemented in
Dispatch Control Register bits 13:6 and 1
SPARC64 V
does not implement DCR.
DCR bits 5:3 and 0
SPARC64 V
does not implement DCR.
Instruction Trap Register
SPARC64 V
implements the Instruction Trap Register.
should not be used, since future versions
2
SPARC64 V
SPARC64 V
.
SPARC64 V
does mask out the high-order 32 bits of
is 8; therefore, only 3 bits are implemented for
SPARC64 V
F. Chapter C
.
1 to any of these
.
Implementation Dependencies
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