Fujitsu SPARC JPS1 Implementation Supplement Manual page 205

2. Otherwise:
D1 Cache Way Reduction
When a way reduction condition is recognized for the D1 cache way W (W = 0 or 1),
the following way reduction procedure is executed:
1. When only one way in D1 cache is active because of previous way reduction:
2. Otherwise:
U2 Cache Way Reduction
When a way reduction condition is recognized for a U2 cache way, the U2 cache way
reduction procedure is executed as follows:
1. When ASI_L2CTL.WEAK_SPCA = 0,
the U2 cache way reduction procedure (below) is started immediately.
2. Otherwise, when ASI_L2CTL.WEAK_SPCA = 1 is set,
the U2 cache way reduction procedure (below) becomes pending until
ASI_L2CTL.WEAK_SPCA is changed to 0. When ASI_L2CTL.WEAK_SPCA is
changed to 0, the U2 cache way reduction procedure will be started.
The U2 cache way W (W=0, 1, 2, or 3) reduction procedure:
1. When only one way in U2 cache is active because of previous way reductions:
194 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
All entries in I1 cache way W are invalidated and the way W will never be
refilled.
The restrainable error
The CPU enters
error_state
All entries in D1 cache way W are invalidated and the way W will never be
refilled. On invalidation of each dirty D1 cache entry, the D1 cache line is
written back to its corresponding U2 cache line.
The restrainable error
All entries in U2 cache way W are at once invalidated (that is, all active U2
cache entries are invalidated) and U2 cache way W remains as the only
available U2 cache way. The U2 cache data is invalidated to retain system
consistency.
The restrainable error
though the available U2 cache configuration is not changed as a result of the
error.
ASI_AFSR.DG_L1$U2$STLB
.
ASI_AFSR.DG_L1$U2$STLB
ASI_AFSR.DG_L1$U2$STLB
is reported to software.
is reported to software.
is reported to software, even