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SPARC64 V and UltraSPARC-III Differences
TABLE T-1
Feature
SPARC64 V
Error status
ASI 4C
SPARC64 V implements an error
status register to indicate where an
error was detected.
Error Control
ASI 4C
Register
SPARC64 V implements a control
register to signal/suppress a trap
when an error was detected.
Multiple registers (VA addressed)
ASI_AFAR
for L1D, L2. 43-bit PA.
ASI device and
ASI 53
serial ID
code for each processor.
I/D SFSR
Many differences.
Error
ASI 6E
Identification
an error ID register. Used to encode
Register (EIDR)
CPU-ID into error marking when
an unrecoverable ECC error occurs.
I-cache and
Not supported.
Branch
Prediction Array
MCU Control
SPARC64 V does not have an
Register
MCU.
Module ID bits
Implements 5-bit IDs.
Performance
SPARC64 V implements a different
counters
set of performance counters than
those of UltraSPARC-III.
Dispatch
SPARC64 V does not have the DCR. 22
Control Register
(DCR)
Version Register
For SPARC64 V:
(VER)
manuf = 0004
impl = 5,
mask = <mask revision number>,
maxtl = 5,
maxwin = 7.
Watchdog reset
Supports
trap
setting OPSR,
is not signalled and CPU stays in
error_state.
Release 1.0, 1 July 2002
/08
(ASI_UGESR):
16
16
/10
(ASI_ECR):
16
16
: provides an identification
16
: SPARC64 V implements
16
,
16
trap. By
watchdog_reset
trap
watchdog_reset
F. Chapter S
Summary of Differences between SPARC64 V and UltraSPARC-III
(3 of 3)
SPARC64 V
Page
UltraSPARC-III
165
Not implemented.
161
Not implemented.
177
Single register, multiple use.
43-bit PA.
119
ASI 53
: ASI_SERIAL_ID
16
97
Many differences.
161
Not implemented.
—
ASIs 66
through 68
16
6F
support instruction cache
16
and branch prediction array
diagnostic access.
—
ASI 72
: MCU Control Register. App. U
16
136
Implements 10-bit IDs.
203
UltraSPARC-III implements a
different set of performance
counters than those of
SPARC64 V.
UltraSPARC-III defines the DCR.
20
For UltraSPARC-III:
manuf = 0017
impl = 0014
mask = <mask revision number>,
maxtl = 5,
maxwin = 7.
140
Supports
watchdog_reset
UltraSPARC-
III Section
—
—
P.4.2
?
Chapter 8
—
and ASI
V.4, V.5
16
R.2
App. Q
5.2.11
C.3.4
,
16
,
16
trap.
O.1
221
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