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Marked Uncorrectable Error in D1 Cache Data
When a marked uncorrectable error (
cache line writeback to the U2 cache, the D1 cache data and its ECC are written to
the target U2 cache data and its ECC without modification. That is, a marked
D1 cache is propagated into the U2 cache. Such an error is not reported to software.
When a marked
(excluding doubleword store) instruction, the data access error is detected. The
data_access_error
its ERROR_MARK_ID are indicated in ASI_DSFSR.
Raw Uncorrectable Error in D1 Cache Data During D1 Cache
Line Writeback
When a raw (unmarked)
writeback to the U2 cache, error marking is applied to the doubleword containing
the raw
doubleword with marked
The restrainable error
Raw Uncorrectable Error in D1 Cache Data on Access by Load
or Store Instruction
When a raw (unmarked)
store instruction, hardware executes the following sequence:
1. Hardware writes back the D1 cache line and refills it from U2 cache. The D1 cache
line containing the raw
the U2 cache. During this D1 cache line writeback to U2 cache, error marking is
applied for the doubleword containing the raw
ERROR_MARK_ID = ASI_EIDR. The D1 cache line is refilled from the U2 cache
and the restrainable error
2. Normally, hardware changes the raw
However, yet another error may introduce a raw
again. When a raw
reduction is applied.
3. At this point, hardware changes the raw
The load or store instruction accesses the doubleword with the marked
marked
described in Raw Uncorrectable Error in D1 Cache Data During D1 Cache Line
Writeback, above.
Release 1.0, 1 July 2002
in D1 cache data is detected during access by a load or store
UE
exception is generated precisely and the marked
is detected in D1 cache data during the D1 cache line
UE
with ERROR_MARK_ID = ASI_EIDR. Only the correct doubleword or the
UE
UE
ASI_AFSR.UE_RAW_D1$INSD
is detected in D1 cache data during access by a load or
UE
, whether it is clean or dirty, is always written back to
UE
ASI_AFSR.UE_RAW_D1$INSD
is detected again, step 1 is repeated until the D1 cache way
UE
is detected during execution of the load or store instruction, as
UE
) in D1 cache data is detected during the D1
UE
is written into the target U2 cache line.
is detected.
UE
in the D1 cache data to a marked
UE
in the D1 cache data to a marked
UE
detection and
UE
with
is detected.
into the same doubleword
UE
F. Chapter P
Error Handling
in
UE
.
UE
.
UE
. The
UE
191
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