Fujitsu SPARC JPS1 Implementation Supplement Manual page 91

TABLE C-1
Nbr
252
253
254
255
256
257
258
80 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
SPARC64 V Implementation Dependencies (11 of 11)
SPARC64 V Implementation Notes
DCUCR.DC (Data Cache Enable)
SPARC64 V
does not implement DCUCR.DC.
DCUCR.IC (Instruction Cache Enable)
SPARC64 V does not implement DCUCR.IC.
Means of exiting error_state
The standard behavior of a
error_state is to reset itself by internally generating a
(WDR). However, OPSR can be set so that when error_state is entered, the
processor remains halted in error_state instead of generating a
.
watchdog_reset
LDDFA with ASI E0 or E1
16
No exception is generated based on the destination register rd.
LDDFA with ASI E0 or E1
16
For LDDFA with ASI E0
16
boundary, a SPARC64 V processor behaves as follows:
n 3 ( 8-byte alignment): no exception related to memory address
alignment is generated.
n = 2 (4-byte alignment):
generated.
n 1 ( 2-byte alignment):
generated.
LDDFA with ASI C0 –C5
16
–
For LDDFA with C0 C5
16
n
a 2 -byte boundary, a SPARC64 V processor behaves as follows:
n 3 ( 8-byte alignment): no exception related to memory address
alignment is generated.
n = 2 (4-byte alignment):
generated.
n 1 ( 2-byte alignment):
generated.
ASI_SERIAL_ID
SPARC64 V provides an identification code for each processor.
SPARC64 V
CPU upon entry into
and misaligned destination register number
16
and misaligned memory address
16
or E1 and a memory address aligned on a 2
1
LDDF_mem_address_not_aligned
mem_address_not_aligned
or –
C8 CD and misaligned memory address
16 16 16
or –
C8 CD and a memory address aligned on
16 16 16
LDDF_mem_address_not_aligned
mem_address_not_aligned
Page
37, 146
watchdog_reset
n
-byte
exception is
exception is
exception is
exception is
24
24
120
120
120
119