Fujitsu SPARC JPS1 Implementation Supplement Manual page 8

Cache Coherency Protocols 128
Cache Control/Status Instructions 128
N. Interrupt Handling 133
Interrupt Dispatch 133
Interrupt Receive 135
Interrupt Global Registers 136
Interrupt-Related ASR Registers 136
O. Reset, RED_state, and error_state 137
Reset Types 137
RED_state and error_state 139
Processor State after Reset and in RED_state 141
P. Error Handling 149
Error Classification 149
Release 1.0, 1 July 2002
Level-1 Data Cache (L1D Cache) 127
Level-2 Unified Cache (L2 Cache) 127
Flush Level-1 Instruction Cache (ASI_FLUSH_L1I) 129
Level-2 Cache Control Register (ASI_L2_CTRL) 130
L2 Diagnostics Tag Read (ASI_L2_DIAG_TAG_READ) 130
L2 Diagnostics Tag Read Registers (ASI_L2_DIAG_TAG_READ_REG) 131
Interrupt Vector Dispatch Register 136
Interrupt Vector Dispatch Status Register 136
Interrupt Vector Receive Register 136
Power-on Reset (POR) 137
Watchdog Reset (WDR) 138
Externally Initiated Reset (XIR) 138
Software-Initiated Reset (SIR) 138
RED_state 140
error_state 140
CPU Fatal Error state 141
Operating Status Register (OPSR) 146
Hardware Power-On Reset Sequence 147
Firmware Initialization Sequence 147
Fatal Error 149
F. Chapter Contents v